From 4ce3b1e4ce69d117f2ac575ae9bbcd3b627fcad9 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Thu, 15 Jan 2015 16:30:07 +0000 Subject: [PATCH] [Hexagon] Replacing old fadd/fsub instructions and updating references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226176 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonISelLowering.cpp | 14 +++++++-- lib/Target/Hexagon/HexagonInstrInfoV5.td | 35 ++++------------------ test/CodeGen/Hexagon/dadd.ll | 2 +- test/CodeGen/Hexagon/dsub.ll | 2 +- 4 files changed, 19 insertions(+), 34 deletions(-) diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index ef5d6b97fd6..cd7f3fdd9b1 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1109,6 +1109,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3"); setOperationAction(ISD::FDIV, MVT::f64, Expand); + setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3"); + setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3"); + setOperationAction(ISD::FSQRT, MVT::f32, Expand); setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::FSIN, MVT::f32, Expand); @@ -1117,7 +1120,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) if (Subtarget.hasV5TOps()) { // Hexagon V5 Support. setOperationAction(ISD::FADD, MVT::f32, Legal); - setOperationAction(ISD::FADD, MVT::f64, Legal); + setOperationAction(ISD::FADD, MVT::f64, Expand); + setOperationAction(ISD::FSUB, MVT::f32, Legal); + setOperationAction(ISD::FSUB, MVT::f64, Expand); setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal); setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal); setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal); @@ -1202,11 +1207,14 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi"); setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi"); - setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3"); - setOperationAction(ISD::FADD, MVT::f64, Expand); setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3"); setOperationAction(ISD::FADD, MVT::f32, Expand); + setOperationAction(ISD::FADD, MVT::f64, Expand); + + setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3"); + setOperationAction(ISD::FSUB, MVT::f32, Expand); + setOperationAction(ISD::FSUB, MVT::f64, Expand); setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2"); setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand); diff --git a/lib/Target/Hexagon/HexagonInstrInfoV5.td b/lib/Target/Hexagon/HexagonInstrInfoV5.td index b0c4305d491..d417d128415 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV5.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV5.td @@ -148,6 +148,12 @@ let isCommutable = 1, isCodeGenOnly = 0 in { let isCodeGenOnly = 0 in def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>; +def: Pat<(f32 (fadd F32:$src1, F32:$src2)), + (F2_sfadd F32:$src1, F32:$src2)>; + +def: Pat<(f32 (fsub F32:$src1, F32:$src2)), + (F2_sfsub F32:$src1, F32:$src2)>; + let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in { def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>; def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>; @@ -489,35 +495,6 @@ def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>; def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>; } -// Add -let isCommutable = 1 in -def fADD_rr : ALU64_rr<(outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2), - "$dst = sfadd($src1, $src2)", - [(set IntRegs:$dst, (fadd IntRegs:$src1, IntRegs:$src2))]>, - Requires<[HasV5T]>; - -let isCommutable = 1 in -def fADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, - DoubleRegs:$src2), - "$dst = dfadd($src1, $src2)", - [(set DoubleRegs:$dst, (fadd DoubleRegs:$src1, - DoubleRegs:$src2))]>, - Requires<[HasV5T]>; - -def fSUB_rr : ALU64_rr<(outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2), - "$dst = sfsub($src1, $src2)", - [(set IntRegs:$dst, (fsub IntRegs:$src1, IntRegs:$src2))]>, - Requires<[HasV5T]>; - -def fSUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, - DoubleRegs:$src2), - "$dst = dfsub($src1, $src2)", - [(set DoubleRegs:$dst, (fsub DoubleRegs:$src1, - DoubleRegs:$src2))]>, - Requires<[HasV5T]>; - let isCommutable = 1 in def fMUL_rr : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), diff --git a/test/CodeGen/Hexagon/dadd.ll b/test/CodeGen/Hexagon/dadd.ll index 602978ac01d..a86a90c89a1 100644 --- a/test/CodeGen/Hexagon/dadd.ll +++ b/test/CodeGen/Hexagon/dadd.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate double precision floating point add in V5. -; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfadd(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}}) +; CHECK: call __hexagon_adddf3 define i32 @main() nounwind { diff --git a/test/CodeGen/Hexagon/dsub.ll b/test/CodeGen/Hexagon/dsub.ll index 4f9d39ed0b2..f271492d057 100644 --- a/test/CodeGen/Hexagon/dsub.ll +++ b/test/CodeGen/Hexagon/dsub.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate double precision floating point subtract in V5. -; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfsub(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}}) +; CHECK: call __hexagon_subdf3 define i32 @main() nounwind { entry: -- 2.34.1