From 4aefd6b7d4dadf8109221a89742725c116d8f8e0 Mon Sep 17 00:00:00 2001 From: Anton Korobeynikov Date: Wed, 20 Feb 2008 12:07:57 +0000 Subject: [PATCH] Fix newly-introduced 4.3 warnings git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47375 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Assembly/Parser.h | 2 +- lib/AsmParser/llvmAsmParser.y | 3 ++- lib/AsmParser/llvmAsmParser.y.cvs | 3 ++- lib/CodeGen/RegAllocLinearScan.cpp | 6 ++++-- lib/CodeGen/RegAllocLocal.cpp | 3 ++- lib/Target/CellSPU/SPUFrameInfo.h | 12 ++++++------ lib/Target/CellSPU/SPURegisterInfo.cpp | 2 +- lib/Target/CellSPU/SPURegisterInfo.h | 2 +- lib/Target/X86/X86RegisterInfo.cpp | 3 ++- lib/Transforms/Scalar/InstructionCombining.cpp | 4 ++-- lib/Transforms/Utils/LCSSA.cpp | 2 +- lib/VMCore/ParameterAttributes.cpp | 2 +- 12 files changed, 25 insertions(+), 19 deletions(-) diff --git a/include/llvm/Assembly/Parser.h b/include/llvm/Assembly/Parser.h index b8d505761f4..edca08c46fb 100644 --- a/include/llvm/Assembly/Parser.h +++ b/include/llvm/Assembly/Parser.h @@ -80,7 +80,7 @@ public: // ParserOptions in effect. If positional information is not applicable, // these will return a value of -1. // - inline const void getErrorLocation(int &Line, int &Column) const { + inline void getErrorLocation(int &Line, int &Column) const { Line = LineNo; Column = ColumnNo; } diff --git a/lib/AsmParser/llvmAsmParser.y b/lib/AsmParser/llvmAsmParser.y index 5a3f17c1470..9e9da4723dc 100644 --- a/lib/AsmParser/llvmAsmParser.y +++ b/lib/AsmParser/llvmAsmParser.y @@ -578,12 +578,13 @@ static BasicBlock *getBBVal(const ValID &ID) { } if (ID.Type == ValID::LocalName) { std::string Name = ID.getName(); Value *N = CurFun.CurrentFunction->getValueSymbolTable().lookup(Name); - if (N) + if (N) { if (N->getType()->getTypeID() == Type::LabelTyID) BB = cast(N); else GenerateError("Reference to label '" + Name + "' is actually of type '"+ N->getType()->getDescription() + "'"); + } } else if (ID.Type == ValID::LocalID) { if (ID.Num < CurFun.NextValNum && ID.Num < CurFun.Values.size()) { if (CurFun.Values[ID.Num]->getType()->getTypeID() == Type::LabelTyID) diff --git a/lib/AsmParser/llvmAsmParser.y.cvs b/lib/AsmParser/llvmAsmParser.y.cvs index 5a3f17c1470..9e9da4723dc 100644 --- a/lib/AsmParser/llvmAsmParser.y.cvs +++ b/lib/AsmParser/llvmAsmParser.y.cvs @@ -578,12 +578,13 @@ static BasicBlock *getBBVal(const ValID &ID) { } if (ID.Type == ValID::LocalName) { std::string Name = ID.getName(); Value *N = CurFun.CurrentFunction->getValueSymbolTable().lookup(Name); - if (N) + if (N) { if (N->getType()->getTypeID() == Type::LabelTyID) BB = cast(N); else GenerateError("Reference to label '" + Name + "' is actually of type '"+ N->getType()->getDescription() + "'"); + } } else if (ID.Type == ValID::LocalID) { if (ID.Num < CurFun.NextValNum && ID.Num < CurFun.Values.size()) { if (CurFun.Values[ID.Num]->getType()->getTypeID() == Type::LabelTyID) diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index c70ff952432..f4f994c9e73 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -224,11 +224,12 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) { unsigned SrcReg, DstReg; if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) return Reg; - if (TargetRegisterInfo::isVirtualRegister(SrcReg)) + if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { if (!vrm_->isAssignedReg(SrcReg)) return Reg; else SrcReg = vrm_->getPhys(SrcReg); + } if (Reg == SrcReg) return Reg; @@ -864,7 +865,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { // If copy coalescer has assigned a "preferred" register, check if it's // available first. - if (cur->preference) + if (cur->preference) { if (prt_->isRegAvail(cur->preference)) { DOUT << "\t\tassigned the preferred register: " << tri_->getName(cur->preference) << "\n"; @@ -872,6 +873,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { } else DOUT << "\t\tunable to assign the preferred register: " << tri_->getName(cur->preference) << "\n"; + } // Scan for the first available register. TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_); diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index b14af2761c6..765e7ff96ff 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -775,11 +775,12 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { // Spill all physical registers holding virtual registers now. for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) - if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) + if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) { if (unsigned VirtReg = PhysRegsUsed[i]) spillVirtReg(MBB, MI, VirtReg, i); else removePhysReg(i); + } #if 0 // This checking code is very expensive. diff --git a/lib/Target/CellSPU/SPUFrameInfo.h b/lib/Target/CellSPU/SPUFrameInfo.h index 91e48416c29..99136c24602 100644 --- a/lib/Target/CellSPU/SPUFrameInfo.h +++ b/lib/Target/CellSPU/SPUFrameInfo.h @@ -34,7 +34,7 @@ namespace llvm { getCalleeSaveSpillSlots(unsigned &NumEntries) const; //! Stack slot size (16 bytes) - static const int stackSlotSize() { + static int stackSlotSize() { return 16; } //! Maximum frame offset representable by a signed 10-bit integer @@ -42,19 +42,19 @@ namespace llvm { This is the maximum frame offset that can be expressed as a 10-bit integer, used in D-form addresses. */ - static const int maxFrameOffset() { + static int maxFrameOffset() { return ((1 << 9) - 1) * stackSlotSize(); } //! Minimum frame offset representable by a signed 10-bit integer - static const int minFrameOffset() { + static int minFrameOffset() { return -(1 << 9) * stackSlotSize(); } //! Minimum frame size (enough to spill LR + SP) - static const int minStackSize() { + static int minStackSize() { return (2 * stackSlotSize()); } //! Frame size required to spill all registers plus frame info - static const int fullSpillSize() { + static int fullSpillSize() { return (SPURegisterInfo::getNumArgRegs() * stackSlotSize()); } //! Number of instructions required to overcome hint-for-branch latency @@ -65,7 +65,7 @@ namespace llvm { of instructions occurs between the HBR and the target. Currently, HBRs take 6 cycles, ergo, the magic number 6. */ - static const int branchHintPenalty() { + static int branchHintPenalty() { return 6; } }; diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index 4a607558141..843760ee5eb 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -221,7 +221,7 @@ SPURegisterInfo::getArgRegs() return SPU_ArgRegs; } -const unsigned +unsigned SPURegisterInfo::getNumArgRegs() { return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]); diff --git a/lib/Target/CellSPU/SPURegisterInfo.h b/lib/Target/CellSPU/SPURegisterInfo.h index f54c11159cd..5520bf36c9c 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.h +++ b/lib/Target/CellSPU/SPURegisterInfo.h @@ -90,7 +90,7 @@ namespace llvm { static const unsigned *getArgRegs(); //! Return the size of the argument passing register array - static const unsigned getNumArgRegs(); + static unsigned getNumArgRegs(); //! Get DWARF debugging register number int getDwarfRegNum(unsigned RegNum, bool isEH) const; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 10a0eec562e..f905ffa4523 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -145,11 +145,12 @@ unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const { const TargetRegisterClass * X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { - if (RC == &X86::CCRRegClass) + if (RC == &X86::CCRRegClass) { if (Is64Bit) return &X86::GR64RegClass; else return &X86::GR32RegClass; + } return NULL; } diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp index 12008956153..d6d87813542 100644 --- a/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/lib/Transforms/Scalar/InstructionCombining.cpp @@ -5481,8 +5481,8 @@ Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI, // Extending a relational comparison when we're checking the sign // bit would not work. if (Cast->hasOneUse() && - (ICI.isEquality() || AndCST->getValue().isNonNegative() && - RHSV.isNonNegative())) { + (ICI.isEquality() || + (AndCST->getValue().isNonNegative() && RHSV.isNonNegative()))) { uint32_t BitWidth = cast(Cast->getOperand(0)->getType())->getBitWidth(); APInt NewCST = AndCST->getValue(); diff --git a/lib/Transforms/Utils/LCSSA.cpp b/lib/Transforms/Utils/LCSSA.cpp index 770ce736da5..567b23e6ffe 100644 --- a/lib/Transforms/Utils/LCSSA.cpp +++ b/lib/Transforms/Utils/LCSSA.cpp @@ -90,7 +90,7 @@ namespace { std::map &Phis); /// inLoop - returns true if the given block is within the current loop - const bool inLoop(BasicBlock* B) { + bool inLoop(BasicBlock* B) { return std::binary_search(LoopBlocks.begin(), LoopBlocks.end(), B); } }; diff --git a/lib/VMCore/ParameterAttributes.cpp b/lib/VMCore/ParameterAttributes.cpp index c49e14c76ed..f67e60d5032 100644 --- a/lib/VMCore/ParameterAttributes.cpp +++ b/lib/VMCore/ParameterAttributes.cpp @@ -186,7 +186,7 @@ ParamAttrsList::includeAttrs(const ParamAttrsList *PAL, // For now, say we can't change a known alignment. ParameterAttributes OldAlign = OldAttrs & ParamAttr::Alignment; ParameterAttributes NewAlign = attrs & ParamAttr::Alignment; - assert(!OldAlign || !NewAlign || OldAlign == NewAlign && + assert((!OldAlign || !NewAlign || OldAlign == NewAlign) && "Attempt to change alignment!"); #endif -- 2.34.1