From 4a0555250d85f2da6f26881ae9c15bcdb49b1d98 Mon Sep 17 00:00:00 2001 From: Alp Toker Date: Sat, 31 May 2014 21:26:28 +0000 Subject: [PATCH] Fix typos git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209982 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 2 +- lib/Support/Host.cpp | 2 +- lib/Target/AArch64/AArch64SchedA53.td | 4 ++-- test/DebugInfo/X86/dbg-value-inlined-parameter.ll | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/CodeGen/AsmPrinter/DwarfUnit.cpp b/lib/CodeGen/AsmPrinter/DwarfUnit.cpp index a70c0f7c11a..29ebad40256 100644 --- a/lib/CodeGen/AsmPrinter/DwarfUnit.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfUnit.cpp @@ -1382,7 +1382,7 @@ DIE *DwarfUnit::getOrCreateSubprogramDIE(DISubprogram SP) { if (DISubprogram SPDecl = SP.getFunctionDeclaration()) { // Add subprogram definitions to the CU die directly. ContextDIE = &getUnitDie(); - // Build the decl now to ensure it preceeds the definition. + // Build the decl now to ensure it precedes the definition. getOrCreateSubprogramDIE(SPDecl); } diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index fd0472ee2f7..ce0a3b6bed7 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -744,7 +744,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) { .Default(""); #if defined(__aarch64__) - // We need to check crypto seperately since we need all of the crypto + // We need to check crypto separately since we need all of the crypto // extensions to enable the subtarget feature if (CPUFeatures[I] == "aes") crypto |= CAP_AES; diff --git a/lib/Target/AArch64/AArch64SchedA53.td b/lib/Target/AArch64/AArch64SchedA53.td index 0c3949ecfc1..d709bee7b9e 100644 --- a/lib/Target/AArch64/AArch64SchedA53.td +++ b/lib/Target/AArch64/AArch64SchedA53.td @@ -148,9 +148,9 @@ def : ReadAdvance; // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable // operands are needed one cycle later if and only if they are to be -// shifted. Otherwise, they too are needed two cycle later. This same +// shifted. Otherwise, they too are needed two cycles later. This same // ReadAdvance applies to Extended registers as well, even though there is -// a seperate SchedPredicate for them. +// a separate SchedPredicate for them. def : ReadAdvance