From 497417520cf9a3b7d4114c1f5f0f21b76d3065c8 Mon Sep 17 00:00:00 2001 From: Elena Demikhovsky Date: Sun, 5 Jan 2014 14:21:07 +0000 Subject: [PATCH] AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD; Optimized a truncate pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198562 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 1 + lib/Target/X86/X86InstrAVX512.td | 50 +++++++++++++++------------- test/CodeGen/X86/avx512-trunc-ext.ll | 10 +++++- 3 files changed, 36 insertions(+), 25 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d4af1eb7a96..005efbb60db 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1363,6 +1363,7 @@ void X86TargetLowering::resetOperationActions() { setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom); setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom); setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom); + setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom); setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 8d9ef8ff1a8..3b7264ae64e 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -99,7 +99,7 @@ def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>; // AVX-512 - VECTOR INSERT // // -- 32x8 form -- -let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in { +let hasSideEffects = 0, ExeDomain = SSEPackedSingle in { def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src1, VR128X:$src2, i8imm:$src3), "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", @@ -112,7 +112,7 @@ def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst), } // -- 64x4 fp form -- -let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in { +let hasSideEffects = 0, ExeDomain = SSEPackedDouble in { def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src1, VR256X:$src2, i8imm:$src3), "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", @@ -124,7 +124,7 @@ def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst), []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>; } // -- 32x4 integer form -- -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src1, VR128X:$src2, i8imm:$src3), "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", @@ -137,7 +137,7 @@ def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst), } -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { // -- 64x4 form -- def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src1, VR256X:$src2, i8imm:$src3), @@ -220,7 +220,7 @@ def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst), //===----------------------------------------------------------------------===// // AVX-512 VECTOR EXTRACT //--- -let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in { +let hasSideEffects = 0, ExeDomain = SSEPackedSingle in { // -- 32x4 form -- def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst), (ins VR512:$src1, i8imm:$src2), @@ -243,7 +243,7 @@ def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs), []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>; } -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { // -- 32x4 form -- def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst), (ins VR512:$src1, i8imm:$src2), @@ -890,7 +890,7 @@ def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1), multiclass avx512_mask_mov opc_kk, bits<8> opc_km, bits<8> opc_mk, string OpcodeStr, RegisterClass KRC, ValueType vt, X86MemOperand x86memop> { - let neverHasSideEffects = 1 in { + let hasSideEffects = 0 in { def kk : I; let mayLoad = 1 in @@ -906,7 +906,7 @@ multiclass avx512_mask_mov opc_kk, bits<8> opc_km, bits<8> opc_mk, multiclass avx512_mask_mov_gpr opc_kr, bits<8> opc_rk, string OpcodeStr, RegisterClass KRC, RegisterClass GRC> { - let neverHasSideEffects = 1 in { + let hasSideEffects = 0 in { def kr : I; def rk : I opc, RegisterClass RC, RegisterClass KRC, X86MemOperand x86memop, PatFrag ld_frag, string asm, Domain d> { -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in def rr : AVX512PI, EVEX; @@ -1245,7 +1245,7 @@ def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$sr SSEPackedDouble>, EVEX, EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>; -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src), "vmovdqa32\t{$src, $dst|$dst, $src}", []>, @@ -1288,7 +1288,7 @@ def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst), multiclass avx512_mov_int load_opc, bits<8> store_opc, string asm, RegisterClass RC, RegisterClass KRC, PatFrag ld_frag, X86MemOperand x86memop> { -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in def rr : AVX512XSI, EVEX; let canFoldAsLoad = 1 in @@ -1452,6 +1452,7 @@ def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), multiclass avx512_move_scalar { + let hasSideEffects = 0 in { def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2), !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR128X:$dst, (vt (OpNode VR128X:$src1, @@ -1471,6 +1472,7 @@ multiclass avx512_move_scalar , EVEX, VEX_LIG; + } //hasSideEffects = 0 } let ExeDomain = SSEPackedSingle in @@ -2496,7 +2498,7 @@ defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X, multiclass avx512_vcvtsi opc, RegisterClass SrcRC, RegisterClass DstRC, X86MemOperand x86memop, string asm> { -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def rr : SI, EVEX_4V; @@ -2505,7 +2507,7 @@ let neverHasSideEffects = 1 in { (ins DstRC:$src1, x86memop:$src), !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, EVEX_4V; -} // neverHasSideEffects = 1 +} // hasSideEffects = 0 } let Predicates = [HasAVX512] in { defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">, @@ -2569,7 +2571,7 @@ def : Pat<(f64 (uint_to_fp GR64:$src)), multiclass avx512_cvt_s_int opc, RegisterClass SrcRC, RegisterClass DstRC, Intrinsic Int, Operand memop, ComplexPattern mem_cpat, string asm> { -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def rr : SI, EVEX, VEX_LIG, @@ -2578,7 +2580,7 @@ let neverHasSideEffects = 1 in { def rm : SI, EVEX, VEX_LIG, Requires<[HasAVX512]>; -} // neverHasSideEffects = 1 +} // hasSideEffects = 0 } let Predicates = [HasAVX512] in { // Convert float/double to signed/unsigned int 32/64 @@ -2709,7 +2711,7 @@ defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem, //===----------------------------------------------------------------------===// // AVX-512 Convert form float to double and back //===----------------------------------------------------------------------===// -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst), (ins FR32X:$src1, FR32X:$src2), "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", @@ -2754,7 +2756,7 @@ multiclass avx512_vcvt_fp_with_rc opc, string asm, RegisterClass SrcRC, RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT, ValueType InVT, Domain d> { -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def rr : AVX512PI, EVEX; -} // neverHasSideEffects = 1 +} // hasSideEffects = 0 } multiclass avx512_vcvt_fp opc, string asm, RegisterClass SrcRC, RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT, ValueType InVT, Domain d> { -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def rr : AVX512PI, EVEX; -} // neverHasSideEffects = 1 +} // hasSideEffects = 0 } defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround, @@ -2872,7 +2874,7 @@ def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src), multiclass avx512_vcvt_fp2int opc, string asm, RegisterClass SrcRC, RegisterClass DstRC, PatFrag mem_frag, X86MemOperand x86memop, Domain d> { -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def rr : AVX512PI, EVEX; @@ -2883,7 +2885,7 @@ let neverHasSideEffects = 1 in { def rm : AVX512PI, EVEX; -} // neverHasSideEffects = 1 +} // hasSideEffects = 0 } defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512, @@ -2931,7 +2933,7 @@ multiclass avx512_f16c_ph2ps, EVEX; - let neverHasSideEffects = 1, mayLoad = 1 in + let hasSideEffects = 0, mayLoad = 1 in def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src), "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX; } @@ -2942,7 +2944,7 @@ multiclass avx512_f16c_ps2ph, EVEX; - let neverHasSideEffects = 1, mayStore = 1 in + let hasSideEffects = 0, mayStore = 1 in def mr : AVX512AIi8<0x1D, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2), "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX; diff --git a/test/CodeGen/X86/avx512-trunc-ext.ll b/test/CodeGen/X86/avx512-trunc-ext.ll index 31db68cc582..9be981c71ce 100644 --- a/test/CodeGen/X86/avx512-trunc-ext.ll +++ b/test/CodeGen/X86/avx512-trunc-ext.ll @@ -116,7 +116,7 @@ define i8 @trunc_8i16_to_8i1(<8 x i16> %a) { ret i8 %mask } -; CHECK: sext_8i1_8i32 +; CHECK-LABEL: sext_8i1_8i32 ; CHECK: vpbroadcastq LCP{{.*}}(%rip), %zmm0 {%k1} {z} ; CHECK: ret define <8 x i32> @sext_8i1_8i32(<8 x i32> %a1, <8 x i32> %a2) nounwind { @@ -125,3 +125,11 @@ define <8 x i32> @sext_8i1_8i32(<8 x i32> %a1, <8 x i32> %a2) nounwind { %y = sext <8 x i1> %x1 to <8 x i32> ret <8 x i32> %y } + +; CHECK-LABEL: trunc_v16i32_to_v16i16 +; CHECK: vpmovdw +; CHECK: ret +define <16 x i16> @trunc_v16i32_to_v16i16(<16 x i32> %x) { + %1 = trunc <16 x i32> %x to <16 x i16> + ret <16 x i16> %1 +} \ No newline at end of file -- 2.34.1