From 47cdf4abff20eb9d7d05406cc1a9be2890ed39bb Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 25 Mar 2010 05:40:48 +0000 Subject: [PATCH] Make the NDEBUG assertion stronger and more clear what is happening. Enhance scheduling to set the DEAD flag on implicit defs more aggressively. Before, we'd set an implicit def operand to dead if it were present in the SDNode corresponding to the machineinstr but had no use. Now we do it in this case AND if the implicit def does not exist in the SDNode at all. This exposes a couple of problems: one is the FIXME, which causes a live intervals crash on CodeGen/X86/sibcall.ll. The second is that it makes machinecse and licm more aggressive (which is a good thing) but also exposes a case where licm hoists a set0 and then it doesn't get resunk. Talking to codegen folks about both these issues, but I need this patch in in the meantime. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99485 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 25 +++++++++++++++---- test/CodeGen/X86/2007-01-13-StackPtrIndex.ll | 1 - test/CodeGen/X86/2009-02-26-MachineLICMBug.ll | 2 +- test/CodeGen/X86/coalesce-esp.ll | 2 +- test/CodeGen/X86/licm-symbol.ll | 2 +- test/CodeGen/X86/phys_subreg_coalesce-2.ll | 2 +- test/CodeGen/X86/pr2659.ll | 2 +- 7 files changed, 25 insertions(+), 11 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 610536fec66..e86a18dc2b4 100644 --- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -578,13 +578,16 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, const TargetInstrDesc &II = TII->get(Opc); unsigned NumResults = CountResults(Node); unsigned NodeOperands = CountOperands(Node); - bool HasPhysRegOuts = (NumResults > II.getNumDefs()) && - II.getImplicitDefs() != 0; + bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; #ifndef NDEBUG unsigned NumMIOperands = NodeOperands + NumResults; - assert((II.getNumOperands() == NumMIOperands || - HasPhysRegOuts || II.isVariadic()) && - "#operands for dag node doesn't match .td file!"); + if (II.isVariadic()) + assert(NumMIOperands >= II.getNumOperands() && + "Too few operands for a variadic node!"); + else + assert(NumMIOperands >= II.getNumOperands() && + NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && + "#operands for dag node doesn't match .td file!"); #endif // Create the new machine instruction. @@ -632,6 +635,18 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, MI->addRegisterDead(Reg, TRI); } } + + // If the instruction has implicit defs and the node doesn't, mark the + // implicit def as dead. If the node has any flag outputs, we don't do this + // because we don't know what implicit defs are being used by flagged nodes. + if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag && + // FIXME: This is a terrible hackaround for a liveintervals bug. + II.getNumImplicitDefs() < 8) + if (const unsigned *IDList = II.getImplicitDefs()) { + for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); + i != e; ++i) + MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); + } return; } diff --git a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll index 5e7c0a7ee2b..a2288986362 100644 --- a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll +++ b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86-64 > %t -; RUN: grep leaq %t ; RUN: not grep {,%rsp)} %t ; PR1103 diff --git a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll index a4d642b4035..ae723f0c299 100644 --- a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll +++ b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& not grep {machine-licm} +; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {2 machine-licm} ; rdar://6627786 target triple = "x86_64-apple-darwin10.0" diff --git a/test/CodeGen/X86/coalesce-esp.ll b/test/CodeGen/X86/coalesce-esp.ll index 0fe4e56c97c..e0f2796f9dc 100644 --- a/test/CodeGen/X86/coalesce-esp.ll +++ b/test/CodeGen/X86/coalesce-esp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep {movl %esp, %eax} +; RUN: llc < %s | grep {movl %esp, %ecx} ; PR4572 ; Don't coalesce with %esp if it would end up putting %esp in diff --git a/test/CodeGen/X86/licm-symbol.ll b/test/CodeGen/X86/licm-symbol.ll index d61bbfccbc9..08306c2950e 100644 --- a/test/CodeGen/X86/licm-symbol.ll +++ b/test/CodeGen/X86/licm-symbol.ll @@ -3,7 +3,7 @@ ; MachineLICM should be able to hoist the sF reference out of the loop. ; CHECK: pushl %esi -; CHECK: subl $8, %esp +; CHECK: subl $4, %esp ; CHECK: movl $176, %esi ; CHECK: addl L___sF$non_lazy_ptr, %esi ; CHECK: .align 4, 0x90 diff --git a/test/CodeGen/X86/phys_subreg_coalesce-2.ll b/test/CodeGen/X86/phys_subreg_coalesce-2.ll index 23c509c9936..60ec2645c28 100644 --- a/test/CodeGen/X86/phys_subreg_coalesce-2.ll +++ b/test/CodeGen/X86/phys_subreg_coalesce-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep mov | count 5 +; RUN: llc < %s -march=x86 | grep mov | count 6 ; PR2659 define i32 @binomial(i32 %n, i32 %k) nounwind { diff --git a/test/CodeGen/X86/pr2659.ll b/test/CodeGen/X86/pr2659.ll index 0760e4c7fd5..01bb9f14f64 100644 --- a/test/CodeGen/X86/pr2659.ll +++ b/test/CodeGen/X86/pr2659.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5 +; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 6 ; PR2659 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -- 2.34.1