From 43638210b855f841f309d35c48fc1dad8ba9f4b1 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 9 Dec 2015 13:48:05 +0000 Subject: [PATCH] [mips][ias] Range check uimm10 operands Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15229 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255112 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 3 +++ lib/Target/Mips/MipsInstrInfo.td | 17 ++++------------- test/MC/Mips/micromips-invalid.s | 5 ----- test/MC/Mips/micromips/invalid.s | 6 ++++++ test/MC/Mips/micromips32r6/invalid.s | 10 ++++++++-- test/MC/Mips/mips32r6/invalid.s | 10 ++++++---- test/MC/Mips/mips64r6/invalid.s | 10 ++++++---- 7 files changed, 33 insertions(+), 28 deletions(-) diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index d04e8d4e4fa..14e63ad0c2b 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3653,6 +3653,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_UImm8_0: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 8-bit unsigned immediate"); + case Match_UImm10_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected 10-bit unsigned immediate"); } llvm_unreachable("Implement any new match types added!"); diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index e3844d67daa..c07edef8673 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -394,8 +394,10 @@ class ConstantUImmAsmOperandClass Supers = [], let DiagnosticType = "UImm" # Bits # "_" # Offset; } +def ConstantUImm10AsmOperandClass + : ConstantUImmAsmOperandClass<10, []>; def ConstantUImm8AsmOperandClass - : ConstantUImmAsmOperandClass<8, []>; + : ConstantUImmAsmOperandClass<8, [ConstantUImm10AsmOperandClass]>; def ConstantUImm6AsmOperandClass : ConstantUImmAsmOperandClass<6, [ConstantUImm8AsmOperandClass]>; def ConstantUImm5Plus32AsmOperandClass @@ -492,17 +494,6 @@ def simm32 : Operand; def uimm20 : Operand { } -def MipsUImm10AsmOperand : AsmOperandClass { - let Name = "UImm10"; - let RenderMethod = "addImmOperands"; - let ParserMethod = "parseImm"; - let PredicateMethod = "isUImm<10>"; -} - -def uimm10 : Operand { - let ParserMatchClass = MipsUImm10AsmOperand; -} - def simm16_64 : Operand { let DecoderMethod = "DecodeSimm16"; } @@ -514,7 +505,7 @@ def uimmz : Operand { } // Unsigned Operands -foreach I = {1, 2, 3, 4, 5, 6, 8} in +foreach I = {1, 2, 3, 4, 5, 6, 8, 10} in def uimm # I : Operand { let PrintMethod = "printUnsignedImm"; let ParserMatchClass = diff --git a/test/MC/Mips/micromips-invalid.s b/test/MC/Mips/micromips-invalid.s index ed0ab1bdc23..60c86987b09 100644 --- a/test/MC/Mips/micromips-invalid.s +++ b/test/MC/Mips/micromips-invalid.s @@ -75,11 +75,6 @@ movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - wait 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction prefx -1, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate prefx 32, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate jraddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 diff --git a/test/MC/Mips/micromips/invalid.s b/test/MC/Mips/micromips/invalid.s index ee5aafc28c9..2bb7886eb2a 100644 --- a/test/MC/Mips/micromips/invalid.s +++ b/test/MC/Mips/micromips/invalid.s @@ -1,6 +1,12 @@ # RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1 # RUN: FileCheck %s < %t1 + break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate + break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate break16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate break16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate diff --git a/test/MC/Mips/micromips32r6/invalid.s b/test/MC/Mips/micromips32r6/invalid.s index 14259eadaea..35f698397ba 100644 --- a/test/MC/Mips/micromips32r6/invalid.s +++ b/test/MC/Mips/micromips32r6/invalid.s @@ -16,8 +16,12 @@ bnezc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction bnezc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range - break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1023, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate + break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate + break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate @@ -68,6 +72,8 @@ tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tltu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tne $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + wait -1 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate + wait 1024 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate wrpgpr $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wrpgpr $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wsbh $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips32r6/invalid.s b/test/MC/Mips/mips32r6/invalid.s index 452cd3a5ee6..ace04085cb7 100644 --- a/test/MC/Mips/mips32r6/invalid.s +++ b/test/MC/Mips/mips32r6/invalid.s @@ -15,10 +15,12 @@ local_label: ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate + break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid.s b/test/MC/Mips/mips64r6/invalid.s index 8d68b51c511..373ad94ad2a 100644 --- a/test/MC/Mips/mips64r6/invalid.s +++ b/test/MC/Mips/mips64r6/invalid.s @@ -13,10 +13,12 @@ local_label: jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate + break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled -- 2.34.1