From 3e8ea1658e264ee7b3c5c52bbbcecaa964ae356a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 3 Nov 2015 22:39:50 +0000 Subject: [PATCH] AMDGPU: Define correct number of SGPRs There are actually 104 so 2 were missing. More assembler tests with high register number tuples will be included in later patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251999 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 ++++ lib/Target/AMDGPU/SIRegisterInfo.td | 12 ++++++------ test/MC/AMDGPU/sop2.s | 3 +++ 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp index 30920a0bb93..1315b6a7b3a 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -41,6 +41,10 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { reserveRegisterTuples(Reserved, AMDGPU::EXEC); reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); + // Reserve the last 2 registers so we will always have at least 2 more that + // will physically contain VCC. + reserveRegisterTuples(Reserved, AMDGPU::SGPR102_SGPR103); + // Tonga and Iceland can only allocate a fixed number of SGPRs due // to a hw bug. if (MF.getSubtarget().hasSGPRInitBug()) { diff --git a/lib/Target/AMDGPU/SIRegisterInfo.td b/lib/Target/AMDGPU/SIRegisterInfo.td index 299c6a69cbd..f7abe53d828 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/lib/Target/AMDGPU/SIRegisterInfo.td @@ -56,7 +56,7 @@ def FLAT_SCR : RegisterWithSubRegs <"flat_scr", [FLAT_SCR_LO, FLAT_SCR_HI]>, } // SGPR registers -foreach Index = 0-101 in { +foreach Index = 0-103 in { def SGPR#Index : SIReg <"SGPR"#Index, Index>; } @@ -75,23 +75,23 @@ foreach Index = 0-255 in { // SGPR 32-bit registers def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32], 32, - (add (sequence "SGPR%u", 0, 101))>; + (add (sequence "SGPR%u", 0, 103))>; // SGPR 64-bit registers def SGPR_64Regs : RegisterTuples<[sub0, sub1], - [(add (decimate (trunc SGPR_32, 101), 2)), + [(add (decimate SGPR_32, 2)), (add (decimate (shl SGPR_32, 1), 2))]>; // SGPR 128-bit registers def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3], - [(add (decimate (trunc SGPR_32, 99), 4)), + [(add (decimate SGPR_32, 4)), (add (decimate (shl SGPR_32, 1), 4)), (add (decimate (shl SGPR_32, 2), 4)), (add (decimate (shl SGPR_32, 3), 4))]>; // SGPR 256-bit registers def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7], - [(add (decimate (trunc SGPR_32, 95), 4)), + [(add (decimate SGPR_32, 4)), (add (decimate (shl SGPR_32, 1), 4)), (add (decimate (shl SGPR_32, 2), 4)), (add (decimate (shl SGPR_32, 3), 4)), @@ -103,7 +103,7 @@ def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7], // SGPR 512-bit registers def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15], - [(add (decimate (trunc SGPR_32, 87), 4)), + [(add (decimate SGPR_32, 4)), (add (decimate (shl SGPR_32, 1), 4)), (add (decimate (shl SGPR_32, 2), 4)), (add (decimate (shl SGPR_32, 3), 4)), diff --git a/test/MC/AMDGPU/sop2.s b/test/MC/AMDGPU/sop2.s index 9a7a1c01064..1fdc47aa616 100644 --- a/test/MC/AMDGPU/sop2.s +++ b/test/MC/AMDGPU/sop2.s @@ -129,3 +129,6 @@ s_cbranch_g_fork s[4:5], s[6:7] // CHECK: s_absdiff_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x96] s_absdiff_i32 s2, s4, s6 + +// CHECK: s_add_u32 s101, s102, s103 ; encoding: [0x66,0x67,0x65,0x80] +s_add_u32 s101, s102, s103 -- 2.34.1