From 3d712a637368048b067d61ce2eeca77bf5c9a653 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 12 Mar 2015 21:34:22 +0000 Subject: [PATCH] R600/SI: Remove _e32 and _e64 suffixes from mnemonics Instead print them as part of the $dst operand. The AsmMatcher requires the 32-bit and 64-bit encodings have the same mnemonic in order to parse them correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232105 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../R600/InstPrinter/AMDGPUInstPrinter.cpp | 10 ++++ .../R600/InstPrinter/AMDGPUInstPrinter.h | 1 + lib/Target/R600/SIInstrFormats.td | 5 +- lib/Target/R600/SIInstrInfo.td | 48 ++++++++++--------- lib/Target/R600/SIInstructions.td | 2 +- test/CodeGen/R600/madak.ll | 4 +- test/CodeGen/R600/madmk.ll | 2 +- test/CodeGen/R600/uint_to_fp.ll | 2 +- 8 files changed, 45 insertions(+), 29 deletions(-) diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp index efac73b5aa4..d62fd3f5949 100644 --- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp +++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp @@ -214,6 +214,16 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) { O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']'; } +void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3) + O << "_e64 "; + else + O << "_e32 "; + + printOperand(MI, OpNo, O); +} + void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) { int32_t SImm = static_cast(Imm); if (SImm >= -16 && SImm <= 64) { diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h index 23376490b04..52897185d8f 100644 --- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h +++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h @@ -49,6 +49,7 @@ private: void printSLC(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printTFE(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printRegOperand(unsigned RegNo, raw_ostream &O); + void printVOPDst(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printImmediate32(uint32_t I, raw_ostream &O); void printImmediate64(uint64_t I, raw_ostream &O); void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index 544e61dde79..4167590360d 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -83,6 +83,9 @@ class Enc64 { int Size = 8; } +class VOPDstOperand : RegisterOperand ; +def VOPDstVCC : VOPDstOperand ; + let Uses = [EXEC] in { class VOPAnyCommon pattern> : @@ -96,7 +99,7 @@ class VOPAnyCommon pattern> : } class VOPCCommon pattern> : - VOPAnyCommon <(outs VCCReg:$dst), ins, asm, pattern> { + VOPAnyCommon <(outs VOPDstVCC:$dst), ins, asm, pattern> { let DisableEncoding = "$dst"; let VOPC = 1; diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 5b0dae3324b..4967da3ec8c 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -287,6 +287,8 @@ def ClampMod : Operand { } // End OperandType = "OPERAND_IMMEDIATE" +def VOPDstS64 : VOPDstOperand ; + //===----------------------------------------------------------------------===// // Complex patterns //===----------------------------------------------------------------------===// @@ -640,9 +642,9 @@ class getNumSrcArgs { // Returns the register class to use for the destination of VOP[123C] // instructions for the given VT. class getVALUDstForVT { - RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, - !if(!eq(VT.Size, 64), VReg_64, - SReg_64)); // else VT == i1 + RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand, + !if(!eq(VT.Size, 64), VOPDstOperand, + VOPDstOperand)); // else VT == i1 } // Returns the register class to use for source 0 of VOP[12C] @@ -720,7 +722,7 @@ class getIns64 { string src1 = ", $src1"; string src2 = ", $src2"; - string ret = " $dst, $src0"# + string ret = "$dst, $src0"# !if(!eq(NumSrcArgs, 1), "", src1)# !if(!eq(NumSrcArgs, 3), src2, ""); } @@ -736,7 +738,7 @@ class getAsm64 { string ret = !if(!eq(HasModifiers, 0), getAsm32.ret, - " $dst, "#src0#src1#src2#"$clamp"#"$omod"); + "$dst, "#src0#src1#src2#"$clamp"#"$omod"); } @@ -748,7 +750,7 @@ class VOPProfile _ArgVT> { field ValueType Src0VT = ArgVT[1]; field ValueType Src1VT = ArgVT[2]; field ValueType Src2VT = ArgVT[3]; - field RegisterClass DstRC = getVALUDstForVT.ret; + field RegisterOperand DstRC = getVALUDstForVT.ret; field RegisterOperand Src0RC32 = getVOPSrc0ForVT.ret; field RegisterClass Src1RC32 = getVOPSrc1ForVT.ret; field RegisterOperand Src0RC64 = getVOP3SrcForVT.ret; @@ -764,7 +766,7 @@ class VOPProfile _ArgVT> { field dag Ins64 = getIns64.ret; - field string Asm32 = "_e32"#getAsm32.ret; + field string Asm32 = getAsm32.ret; field string Asm64 = getAsm64.ret; } @@ -791,12 +793,12 @@ def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> { def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> { let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); - let Asm64 = " $dst, $src0_modifiers, $src1"; + let Asm64 = "$dst, $src0_modifiers, $src1"; } def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> { let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); - let Asm64 = " $dst, $src0_modifiers, $src1"; + let Asm64 = "$dst, $src0_modifiers, $src1"; } def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>; @@ -805,13 +807,13 @@ def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>; def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> { let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2); let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2); - let Asm64 = " $dst, $src0, $src1, $src2"; + let Asm64 = "$dst, $src0, $src1, $src2"; } def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>; def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> { field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2); - field string Asm = " $dst, $src0, $vsrc1, $src2"; + field string Asm = "$dst, $src0, $vsrc1, $src2"; } def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>; def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>; @@ -1094,7 +1096,7 @@ multiclass VOP1_Helper ; - defm _e64 : VOP3_1_m ; + defm _e64 : VOP3_1_m ; } multiclass VOP1Inst ; defm _e64 : VOP3_2_m ; } @@ -1153,7 +1155,7 @@ multiclass VOP2InstSI { defm _e32 : VOP2SI_m ; - defm _e64 : VOP3SI_2_m ; defm _e64 : VOP3b_2_m ; } @@ -1197,7 +1199,7 @@ multiclass VOP2_VI3_Helper { defm _e32 : VOP2SI_m ; - defm _e64 : VOP3_2_m ; } @@ -1263,7 +1265,7 @@ multiclass VOPC_Helper { defm _e32 : VOPC_m ; - defm _e64 : VOP3_C_m ; } @@ -1275,7 +1277,7 @@ multiclass VOPC_Class_Helper { defm _e32 : VOPC_m ; - defm _e64 : VOP3_C_m , VOP3DisableModFields<1, 0, 0>; } @@ -1285,7 +1287,7 @@ multiclass VOPCInst : VOPC_Helper < op, opName, P.Ins32, P.Asm32, [], - (outs SReg_64:$dst), P.Ins64, P.Asm64, + (outs VOPDstS64:$dst), P.Ins64, P.Asm64, !if(P.HasModifiers, [(set i1:$dst, (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, @@ -1300,7 +1302,7 @@ multiclass VOPCClassInst : VOPC_Class_Helper < op, opName, P.Ins32, P.Asm32, [], - (outs SReg_64:$dst), P.Ins64, P.Asm64, + (outs VOPDstS64:$dst), P.Ins64, P.Asm64, !if(P.HasModifiers, [(set i1:$dst, (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))], @@ -1340,7 +1342,7 @@ multiclass VOPCX_I64 : multiclass VOP3_Helper pat, int NumSrcArgs, bit HasMods> : VOP3_m < - op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods + op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods >; multiclass VOPC_CLASS_F32 : @@ -1357,7 +1359,7 @@ multiclass VOPCX_CLASS_F64 : multiclass VOP3Inst : VOP3_Helper < - op, opName, P.Outs, P.Ins64, P.Asm64, + op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64, !if(!eq(P.NumSrcArgs, 3), !if(P.HasModifiers, [(set P.DstVT:$dst, @@ -1389,7 +1391,7 @@ multiclass VOP3_VCC_Inst : VOP3_Helper < op, opName, - P.Outs, + (outs P.DstRC.RegClass:$dst), (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0, InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1, InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2, diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index cf9c310f86b..5f02a31f67c 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1490,7 +1490,7 @@ multiclass V_CNDMASK { defm _e64 : VOP3_m < op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins64, - name#"_e64"#!cast(VOP_CNDMASK.Asm64), [], name, 3>; + name#!cast(VOP_CNDMASK.Asm64), [], name, 3>; } defm V_CNDMASK_B32 : V_CNDMASK, "v_cndmask_b32">; diff --git a/test/CodeGen/R600/madak.ll b/test/CodeGen/R600/madak.ll index cc3e91ee7d4..933bb016d2c 100644 --- a/test/CodeGen/R600/madak.ll +++ b/test/CodeGen/R600/madak.ll @@ -9,7 +9,7 @@ declare float @llvm.fabs.f32(float) nounwind readnone ; GCN-LABEL: {{^}}madak_f32: ; GCN: buffer_load_dword [[VA:v[0-9]+]] ; GCN: buffer_load_dword [[VB:v[0-9]+]] -; GCN: v_madak_f32 {{v[0-9]+}}, [[VB]], [[VA]], 0x41200000 +; GCN: v_madak_f32_e32 {{v[0-9]+}}, [[VB]], [[VA]], 0x41200000 define void @madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid @@ -63,7 +63,7 @@ define void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1 ; GCN-LABEL: {{^}}madak_m_inline_imm_f32: ; GCN: buffer_load_dword [[VA:v[0-9]+]] -; GCN: v_madak_f32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000 +; GCN: v_madak_f32_e32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000 define void @madak_m_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a) nounwind { %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid diff --git a/test/CodeGen/R600/madmk.ll b/test/CodeGen/R600/madmk.ll index 17d1b8a3707..71615e9a025 100644 --- a/test/CodeGen/R600/madmk.ll +++ b/test/CodeGen/R600/madmk.ll @@ -7,7 +7,7 @@ declare float @llvm.fabs.f32(float) nounwind readnone ; GCN-LABEL: {{^}}madmk_f32: ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 -; GCN: v_madmk_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000 +; GCN: v_madmk_f32_e32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000 define void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll index d3f02819d1b..00fea80b1bc 100644 --- a/test/CodeGen/R600/uint_to_fp.ll +++ b/test/CodeGen/R600/uint_to_fp.ll @@ -50,7 +50,7 @@ define void @uint_to_fp_v4i32_to_v4f32(<4 x float> addrspace(1)* %out, <4 x i32> ; R600: MULADD_IEEE ; SI: v_cvt_f32_u32_e32 ; SI: v_cvt_f32_u32_e32 -; SI: v_madmk_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x4f800000 +; SI: v_madmk_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x4f800000 ; SI: s_endpgm define void @uint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 %in) { entry: -- 2.34.1