From 3c4a4ffa3dba5e3c7a0900d0bafe28d7095f3ada Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 12 Nov 2008 07:18:38 +0000 Subject: [PATCH] Consolidate formats; fix FCMPED etc. encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59107 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMCodeEmitter.cpp | 125 +++++++++++------------------- lib/Target/ARM/ARMInstrFormats.td | 41 +++++----- lib/Target/ARM/ARMInstrInfo.h | 47 ++++++----- lib/Target/ARM/ARMInstrInfo.td | 60 +++++++------- lib/Target/ARM/ARMInstrVFP.td | 15 ++-- 5 files changed, 120 insertions(+), 168 deletions(-) diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index e36f0e1cb78..c842a961efc 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -312,16 +312,13 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { case ARMII::DPSoRegFrm: emitDataProcessingInstruction(MI); break; - case ARMII::LdFrm: - case ARMII::StFrm: + case ARMII::LdStFrm: emitLoadStoreInstruction(MI); break; - case ARMII::LdMiscFrm: - case ARMII::StMiscFrm: + case ARMII::LdStMiscFrm: emitMiscLoadStoreInstruction(MI); break; - case ARMII::LdMulFrm: - case ARMII::StMulFrm: + case ARMII::LdStMulFrm: emitLoadStoreMultipleInstruction(MI); break; case ARMII::MulFrm: @@ -1040,63 +1037,6 @@ void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { emitWordLE(Binary); } -void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); - - // Part of binary is determined by TableGn. - unsigned Binary = getBinaryCodeForInstr(MI); - - // Set the conditional execution predicate - Binary |= II->getPredicate(&MI) << ARMII::CondShift; - - unsigned OpIdx = 0; - assert((Binary & ARMII::D_BitShift) == 0 && - (Binary & ARMII::N_BitShift) == 0 && - (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); - - // Encode Dd / Sd. - unsigned RegD = MI.getOperand(OpIdx++).getReg(); - bool isSPVFP = false; - RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); - if (!isSPVFP) - Binary |= RegD << ARMII::RegRdShift; - else { - Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; - Binary |= (RegD & 0x01) << ARMII::D_BitShift; - } - - - // If this is a two-address operand, skip it, e.g. FMACD. - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) - ++OpIdx; - - // Encode Dn / Sn. - if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) { - unsigned RegN = MI.getOperand(OpIdx++).getReg(); - isSPVFP = false; - RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP); - if (!isSPVFP) - Binary |= RegN << ARMII::RegRnShift; - else { - Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; - Binary |= (RegN & 0x01) << ARMII::N_BitShift; - } - } - - // Encode Dm / Sm. - unsigned RegM = MI.getOperand(OpIdx++).getReg(); - isSPVFP = false; - RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP); - if (!isSPVFP) - Binary |= RegM; - else { - Binary |= ((RegM & 0x1E) >> 1); - Binary |= (RegM & 0x01) << ARMII::M_BitShift; - } - - emitWordLE(Binary); -} - static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { unsigned RegD = MI.getOperand(OpIdx).getReg(); unsigned Binary = 0; @@ -1139,6 +1079,45 @@ static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { return Binary; } +void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { + const TargetInstrDesc &TID = MI.getDesc(); + + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + unsigned OpIdx = 0; + assert((Binary & ARMII::D_BitShift) == 0 && + (Binary & ARMII::N_BitShift) == 0 && + (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); + + // Encode Dd / Sd. + Binary |= encodeVFPRd(MI, OpIdx++); + + // If this is a two-address operand, skip it, e.g. FMACD. + if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + ++OpIdx; + + // Encode Dn / Sn. + if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) + Binary |= encodeVFPRn(MI, OpIdx); + + if (OpIdx == TID.getNumOperands() || + TID.OpInfo[OpIdx].isPredicate() || + TID.OpInfo[OpIdx].isOptionalDef()) { + // FCMPEZD etc. has only one operand. + emitWordLE(Binary); + return; + } + + // Encode Dm / Sm. + Binary |= encodeVFPRm(MI, OpIdx); + + emitWordLE(Binary); +} + void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); unsigned Form = TID.TSFlags & ARMII::FormMask; @@ -1204,15 +1183,7 @@ void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { unsigned OpIdx = 0; // Encode Dd / Sd. - unsigned RegD = MI.getOperand(OpIdx++).getReg(); - bool isSPVFP = false; - RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); - if (!isSPVFP) - Binary |= RegD << ARMII::RegRdShift; - else { - Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; - Binary |= (RegD & 0x01) << ARMII::D_BitShift; - } + Binary |= encodeVFPRd(MI, OpIdx++); // Encode address base. const MachineOperand &Base = MI.getOperand(OpIdx++); @@ -1257,15 +1228,7 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { Binary |= 0x1 << ARMII::W_BitShift; // First register is encoded in Dd. - unsigned RegD = MI.getOperand(4).getReg(); - bool isSPVFP = false; - RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); - if (!isSPVFP) - Binary |= RegD << ARMII::RegRdShift; - else { - Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; - Binary |= (RegD & 0x01) << ARMII::D_BitShift; - } + Binary |= encodeVFPRd(MI, 4); // Number of registers are encoded in offset field. unsigned NumRegs = 1; diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 6ca931d6939..192dfdf3dba 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -27,28 +27,25 @@ def BrMiscFrm : Format<4>; def DPFrm : Format<5>; def DPSoRegFrm : Format<6>; -def LdFrm : Format<7>; -def StFrm : Format<8>; -def LdMiscFrm : Format<9>; -def StMiscFrm : Format<10>; -def LdMulFrm : Format<11>; -def StMulFrm : Format<12>; - -def ArithMiscFrm : Format<13>; -def ExtFrm : Format<14>; - -def VFPUnaryFrm : Format<15>; -def VFPBinaryFrm : Format<16>; -def VFPConv1Frm : Format<17>; -def VFPConv2Frm : Format<18>; -def VFPConv3Frm : Format<19>; -def VFPConv4Frm : Format<20>; -def VFPConv5Frm : Format<21>; -def VFPLdStFrm : Format<22>; -def VFPLdStMulFrm : Format<23>; -def VFPMiscFrm : Format<24>; - -def ThumbFrm : Format<25>; +def LdStFrm : Format<7>; +def LdStMiscFrm : Format<8>; +def LdStMulFrm : Format<9>; + +def ArithMiscFrm : Format<10>; +def ExtFrm : Format<11>; + +def VFPUnaryFrm : Format<12>; +def VFPBinaryFrm : Format<13>; +def VFPConv1Frm : Format<14>; +def VFPConv2Frm : Format<15>; +def VFPConv3Frm : Format<16>; +def VFPConv4Frm : Format<17>; +def VFPConv5Frm : Format<18>; +def VFPLdStFrm : Format<19>; +def VFPLdStMulFrm : Format<20>; +def VFPMiscFrm : Format<21>; + +def ThumbFrm : Format<22>; // Misc flag for data processing instructions that indicates whether // the instruction has a Rn register operand. diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index d9ee5fcc995..4a0065dce51 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -73,47 +73,44 @@ namespace ARMII { FormMask = 0x1f << FormShift, // Pseudo instructions - Pseudo = 1 << FormShift, + Pseudo = 1 << FormShift, // Multiply instructions - MulFrm = 2 << FormShift, + MulFrm = 2 << FormShift, // Branch instructions - BrFrm = 3 << FormShift, - BrMiscFrm = 4 << FormShift, + BrFrm = 3 << FormShift, + BrMiscFrm = 4 << FormShift, // Data Processing instructions - DPFrm = 5 << FormShift, - DPSoRegFrm = 6 << FormShift, + DPFrm = 5 << FormShift, + DPSoRegFrm = 6 << FormShift, // Load and Store - LdFrm = 7 << FormShift, - StFrm = 8 << FormShift, - LdMiscFrm = 9 << FormShift, - StMiscFrm = 10 << FormShift, - LdMulFrm = 11 << FormShift, - StMulFrm = 12 << FormShift, + LdStFrm = 7 << FormShift, + LdStMiscFrm = 8 << FormShift, + LdStMulFrm = 9 << FormShift, // Miscellaneous arithmetic instructions - ArithMiscFrm = 13 << FormShift, + ArithMiscFrm = 10 << FormShift, // Extend instructions - ExtFrm = 14 << FormShift, + ExtFrm = 11 << FormShift, // VFP formats - VFPUnaryFrm = 15 << FormShift, - VFPBinaryFrm = 16 << FormShift, - VFPConv1Frm = 17 << FormShift, - VFPConv2Frm = 18 << FormShift, - VFPConv3Frm = 19 << FormShift, - VFPConv4Frm = 20 << FormShift, - VFPConv5Frm = 21 << FormShift, - VFPLdStFrm = 22 << FormShift, - VFPLdStMulFrm = 23 << FormShift, - VFPMiscFrm = 24 << FormShift, + VFPUnaryFrm = 12 << FormShift, + VFPBinaryFrm = 13 << FormShift, + VFPConv1Frm = 14 << FormShift, + VFPConv2Frm = 15 << FormShift, + VFPConv3Frm = 16 << FormShift, + VFPConv4Frm = 17 << FormShift, + VFPConv5Frm = 18 << FormShift, + VFPLdStFrm = 19 << FormShift, + VFPLdStMulFrm = 20 << FormShift, + VFPMiscFrm = 21 << FormShift, // Thumb format - ThumbFrm = 25 << FormShift, + ThumbFrm = 22 << FormShift, //===------------------------------------------------------------------===// // Field shifts - such shifts are used to set field while generating diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index b4677f09bc3..d4588dd12ef 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -533,7 +533,7 @@ let isReturn = 1, isTerminator = 1 in let isReturn = 1, isTerminator = 1 in def LDM_RET : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), - LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1", + LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", []>; let isCall = 1, @@ -615,134 +615,134 @@ let isBranch = 1, isTerminator = 1 in { // Load let isSimpleLoad = 1 in -def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, +def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm, "ldr", " $dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; // Special LDR for loads from non-pc-relative constpools. let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in -def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, +def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm, "ldr", " $dst, $addr", []>; // Loads with zero extension -def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, +def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, "ldr", "h $dst, $addr", [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; -def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, +def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdStFrm, "ldr", "b $dst, $addr", [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; // Loads with sign extension -def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, +def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, "ldr", "sh $dst, $addr", [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; -def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, +def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, "ldr", "sb $dst, $addr", [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; let mayLoad = 1 in { // Load doubleword -def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, +def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdStMiscFrm, "ldr", "d $dst, $addr", []>, Requires<[IsARM, HasV5T]>; // Indexed loads def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode2:$addr), LdFrm, + (ins addrmode2:$addr), LdStFrm, "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base, am2offset:$offset), LdFrm, + (ins GPR:$base, am2offset:$offset), LdStFrm, "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode3:$addr), LdMiscFrm, + (ins addrmode3:$addr), LdStMiscFrm, "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdMiscFrm, + (ins GPR:$base,am3offset:$offset), LdStMiscFrm, "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode2:$addr), LdFrm, + (ins addrmode2:$addr), LdStFrm, "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am2offset:$offset), LdFrm, + (ins GPR:$base,am2offset:$offset), LdStFrm, "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode3:$addr), LdMiscFrm, + (ins addrmode3:$addr), LdStMiscFrm, "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdMiscFrm, + (ins GPR:$base,am3offset:$offset), LdStMiscFrm, "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), - (ins addrmode3:$addr), LdMiscFrm, + (ins addrmode3:$addr), LdStMiscFrm, "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), - (ins GPR:$base,am3offset:$offset), LdMiscFrm, + (ins GPR:$base,am3offset:$offset), LdStMiscFrm, "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; } // Store -def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, +def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), LdStFrm, "str", " $src, $addr", [(store GPR:$src, addrmode2:$addr)]>; // Stores with truncate -def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, +def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), LdStMiscFrm, "str", "h $src, $addr", [(truncstorei16 GPR:$src, addrmode3:$addr)]>; -def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, +def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), LdStFrm, "str", "b $src, $addr", [(truncstorei8 GPR:$src, addrmode2:$addr)]>; // Store doubleword let mayStore = 1 in -def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, +def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), LdStMiscFrm, "str", "d $src, $addr", []>, Requires<[IsARM, HasV5T]>; // Indexed stores def STR_PRE : AI2stwpr<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm, + (ins GPR:$src, GPR:$base, am2offset:$offset), LdStFrm, "str", " $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; def STR_POST : AI2stwpo<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + (ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm, "str", " $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; def STRH_PRE : AI3sthpr<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, + (ins GPR:$src, GPR:$base,am3offset:$offset), LdStMiscFrm, "str", "h $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; def STRH_POST: AI3sthpo<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, + (ins GPR:$src, GPR:$base,am3offset:$offset), LdStMiscFrm, "str", "h $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti16 GPR:$src, GPR:$base, am3offset:$offset))]>; def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + (ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm, "str", "b $src, [$base, $offset]!", "$base = $base_wb", [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; def STRB_POST: AI2stbpo<(outs GPR:$base_wb), - (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + (ins GPR:$src, GPR:$base,am2offset:$offset), LdStFrm, "str", "b $src, [$base], $offset", "$base = $base_wb", [(set GPR:$base_wb, (post_truncsti8 GPR:$src, GPR:$base, am2offset:$offset))]>; @@ -755,13 +755,13 @@ def STRB_POST: AI2stbpo<(outs GPR:$base_wb), let mayLoad = 1 in def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), - LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1", + LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", []>; let mayStore = 1 in def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), - StMulFrm, "stm${p}${addr:submode} $addr, $src1", + LdStMulFrm, "stm${p}${addr:submode} $addr, $src1", []>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 5c5b9e28f9b..07e821dbdb7 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -102,19 +102,14 @@ def FADDS : ASbI<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b), "fadds", " $dst, $a, $b", [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>; -def FCMPED : ADbI<0b11101011, (outs), (ins DPR:$a, DPR:$b), +// These are encoded as unary instructions. +def FCMPED : ADuI<0b11101011, 0b0100, 0b1100, (outs), (ins DPR:$a, DPR:$b), "fcmped", " $a, $b", - [(arm_cmpfp DPR:$a, DPR:$b)]> { - let Inst{19-16} = 0b0100; - let Inst{7-6} = 0b11; -} + [(arm_cmpfp DPR:$a, DPR:$b)]>; -def FCMPES : ASbI<0b11101011, (outs), (ins SPR:$a, SPR:$b), +def FCMPES : ASuI<0b11101011, 0b0100, 0b1100, (outs), (ins SPR:$a, SPR:$b), "fcmpes", " $a, $b", - [(arm_cmpfp SPR:$a, SPR:$b)]> { - let Inst{19-16} = 0b0100; - let Inst{7-6} = 0b11; -} + [(arm_cmpfp SPR:$a, SPR:$b)]>; def FDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b), "fdivd", " $dst, $a, $b", -- 2.34.1