From 3b1259bb9f2a903bbc990c9b4f1ecc33eb4f19bf Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Thu, 28 May 2009 02:04:00 +0000 Subject: [PATCH] "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but the Intel manual (screenshot) says it should be 0b11110110 (f6). The existing encoding causes a disassembly conflict with MMX_PAVGBrm, which really should be 0f e0." Patch by Sean Callanan! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72508 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrMMX.td | 2 +- lib/Target/X86/X86InstrSSE.td | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index 338b9e294b4..8f287e17dc3 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -258,7 +258,7 @@ defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>; defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>; defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>; -defm MMX_PSADBW : MMXI_binop_rm_int<0xE0, "psadbw", int_x86_mmx_psad_bw, 1>; +defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>; // Logical Instructions defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>; diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 1cdb40652ea..2e791a8b122 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -1908,7 +1908,7 @@ defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>; defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>; defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>; defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>; -defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>; +defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>; defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", -- 2.34.1