From 3883cba7933554b09cc6c791807eb9f8e7fee4c2 Mon Sep 17 00:00:00 2001 From: Gabor Greif Date: Sun, 11 Oct 2009 10:27:57 +0000 Subject: [PATCH] fix some obvious typos git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83768 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/ReleaseNotes-2.6.html | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/ReleaseNotes-2.6.html b/docs/ReleaseNotes-2.6.html index 708b7947559..78d3d3b3596 100644 --- a/docs/ReleaseNotes-2.6.html +++ b/docs/ReleaseNotes-2.6.html @@ -650,7 +650,7 @@ it run faster:

from the compiler. It works well for many simple C testcases, but doesn't support exception handling, debug info, inline assembly, etc.
  • Targets can now specify register allocation hints through - MachineRegisterInfo:: setRegAllocationHint. A regalloc hint consists of hint + MachineRegisterInfo::setRegAllocationHint. A regalloc hint consists of hint type and physical register number. A hint type of zero specifies a register allocation preference. Other hint type values are target specific which are resolved by TargetRegisterInfo::ResolveRegAllocHint. An example is the ARM @@ -675,7 +675,7 @@ it run faster:

    by OS kernels.
  • X86-64 now models implicit zero extensions better, which allows the code generator to remove a lot of redundant zexts. It also models the 8-bit "H" - registers as sugregs, which allows they to be used in some tricky + registers as sugregs, which allows them to be used in some tricky situations.
  • X86-64 now supports the "local exec" and "initial exec" thread local storage model.
    • @@ -741,8 +741,8 @@ supports both the Thumb2 and Advanced SIMD (Neon) instruction sets.
  • The AAPCS-VFP "hard float" calling conventions are also supported with the -float-abi=hard flag.
    • -
  • The ARM calling convention code is now tblgen generated instead of C++ - code.
    • +
  • The ARM calling convention code is now tblgen generated instead of resorting + to C++ code.
    • -- 2.34.1