From 37b9a19653bfa8cbc6047236f563a3d1dccbadf4 Mon Sep 17 00:00:00 2001 From: Mon P Wang Date: Wed, 11 Mar 2009 06:35:11 +0000 Subject: [PATCH] Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66645 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 5 ++++- test/CodeGen/X86/vec_shuffle-36.ll | 9 +++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/X86/vec_shuffle-36.ll diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 571fd29fef6..3e790b47ed5 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -3630,8 +3630,11 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2, // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the // source words for the shuffle, to aid later transformations. bool AllWordsInNewV = true; + bool InOrder[2] = { true, true }; for (unsigned i = 0; i != 8; ++i) { int idx = MaskVals[i]; + if (idx != (int)i) + InOrder[i/4] = false; if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) continue; AllWordsInNewV = false; @@ -3658,7 +3661,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2, // If we've eliminated the use of V2, and the new mask is a pshuflw or // pshufhw, that's as cheap as it gets. Return the new shuffle. - if (pshufhw || pshuflw) { + if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { MaskV.clear(); for (unsigned i = 0; i != 8; ++i) MaskV.push_back((MaskVals[i] < 0) ? DAG.getUNDEF(MVT::i16) diff --git a/test/CodeGen/X86/vec_shuffle-36.ll b/test/CodeGen/X86/vec_shuffle-36.ll new file mode 100644 index 00000000000..00511870585 --- /dev/null +++ b/test/CodeGen/X86/vec_shuffle-36.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -o %t -f +; RUN: grep pshufb %t | count 1 + + +define <8 x i16> @shuf6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { +entry: + %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 3, i32 2, i32 0, i32 2, i32 1, i32 5, i32 6 , i32 undef > + ret <8 x i16> %tmp9 +} -- 2.34.1