From 349db1738d58d52cae2ab1e06cbd128dd9f0aab6 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 2 Jul 2008 17:01:57 +0000 Subject: [PATCH] instead of aborting on shifts of i1, just implicitly fold them. The dag combiner can produce a shift of i1 when folding icmp i1's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53030 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 0a23966f31f..b22bf1dc621 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2192,7 +2192,13 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, assert(VT == N1.getValueType() && "Shift operators return type must be the same as their first arg"); assert(VT.isInteger() && N2.getValueType().isInteger() && - VT != MVT::i1 && "Shifts only work on integers"); + "Shifts only work on integers"); + + // Always fold shifts of i1 values so the code generator doesn't need to + // handle them. Since we know the size of the shift has to be less than the + // size of the value, the shift/rotate count is guaranteed to be zero. + if (VT == MVT::i1) + return N1; break; case ISD::FP_ROUND_INREG: { MVT EVT = cast(N2)->getVT(); -- 2.34.1