From 341223ee0a769d10adf77acf3e7104164094d4bf Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sun, 18 Jan 2015 15:59:44 +0000 Subject: [PATCH] [PowerPC] Don't hard-code R2 as register when processing TOC relocations Instructions that have high-order TOC relocations always carry R2 as their base register, so it does not matter whether we take the register from the instruction or just hard-code it in PPCAsmPrinter. In the future, however, we might want to apply these relocations to instructions using a different register, so taking the register from the instruction is a better thing to do. No change in functionality here, however. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226403 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCAsmPrinter.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 49fd2f904a2..554ea2ffb90 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -699,7 +699,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { OutContext); EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8) .addReg(MI->getOperand(0).getReg()) - .addReg(PPC::X2) + .addReg(MI->getOperand(1).getReg()) .addExpr(SymGotTprel)); return; } @@ -778,7 +778,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { OutContext); EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8) .addReg(MI->getOperand(0).getReg()) - .addReg(PPC::X2) + .addReg(MI->getOperand(1).getReg()) .addExpr(SymGotTlsGD)); return; } @@ -815,7 +815,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { OutContext); EmitToStreamer(OutStreamer, MCInstBuilder(PPC::ADDIS8) .addReg(MI->getOperand(0).getReg()) - .addReg(PPC::X2) + .addReg(MI->getOperand(1).getReg()) .addExpr(SymGotTlsLD)); return; } -- 2.34.1