From 32e89f2b922aae3d6a99428ae3d1c96304f05e1d Mon Sep 17 00:00:00 2001
From: Chris Lattner
Important Note: For historical reasons, the LLVM SparcV9 code generator uses almost entirely different code paths than described in this document. For this reason, there are some deprecated interfaces (such as -TargetRegInfo and TargetSchedInfo), which are only used by the +TargetSchedInfo), which are only used by the V9 backend and should not be used by any other targets. Also, all code in the lib/Target/SparcV9 directory and subdirectories should be considered deprecated, and should not be used as the basis for future code generator work. @@ -185,36 +193,44 @@ quality code generation for standard register-based microprocessors. Code generation in this model is divided into the following stages:
As LLVM continues to be developed and refined, we plan to move more and more +of the target description to be in .td form. Doing so gives us a +number of advantages. The most important is that it makes it easier to port +LLVM, because it reduces the amount of C++ code that has to be written and the +surface area of the code generator that needs to be understood before someone +can get in an get something working. Second, it is also important to us because +it makes it easier to change things: in particular, if tables and other things +are all emitted by tblgen, we only need to change one place (tblgen) to update +all of the targets to a new interface.
+ @@ -274,8 +300,7 @@ repetition. target machine; independent of any particular client. These classes are designed to capture the abstract properties of the target (such as the instructions and registers it has), and do not incorporate any particular pieces -of code generation algorithms. These interfaces do not take interference graphs -as inputs or other algorithm-specific data structures. +of code generation algorithms.All of the target description classes (except the TargetData class) are designed to be subclassed by @@ -315,8 +340,8 @@ implemented as well.
The TargetData class is the only required target description class, -and it is the only class that is not extensible. You cannot derived a new -class from it. TargetData specifies information about how the target +and it is the only class that is not extensible (you cannot derived a new +class from it). TargetData specifies information about how the target lays out memory for structures, the alignment requirements for various data types, the size of pointers in the target, and whether the target is little-endian or big-endian.
@@ -333,18 +358,16 @@ little-endian or big-endian.The TargetLowering class is used by SelectionDAG based instruction selectors primarily to describe how LLVM code should be lowered to SelectionDAG operations. Among other things, this class indicates: -
Registers in the code generator are represented in the code generator by unsigned numbers. Physical registers (those that actually exist in the target description) are unique small numbers, and virtual registers are generally -large.
+large. Note that register #0 is reserved as a flag value.Each register in the processor description has an associated TargetRegisterDesc entry, which provides a textual name for the register @@ -438,7 +461,8 @@ href="TableGenFundamentals.html">TableGen description of the register file.
At the high-level, LLVM code is translated to a machine specific representation -formed out of MachineFunction, MachineBasicBlock, and MachineFunction, +MachineBasicBlock, and MachineInstr instances (defined in include/llvm/CodeGen). This representation is completely target agnostic, representing instructions in their most abstract form: an opcode and a @@ -624,6 +648,43 @@ are no virtual registers left in the code.
The MachineBasicBlock class contains a list of machine instructions +(MachineInstr instances). It roughly corresponds to +the LLVM code input to the instruction selector, but there can be a one-to-many +mapping (i.e. one LLVM basic block can map to multiple machine basic blocks). +The MachineBasicBlock class has a "getBasicBlock" method, which returns +the LLVM basic block that it comes from. +
+ +The MachineFunction class contains a list of machine basic blocks +(MachineBasicBlock instances). It corresponds +one-to-one with the LLVM function input to the instruction selector. In +addition to a list of basic blocks, the MachineFunction contains a +the MachineConstantPool, MachineFrameInfo, MachineFunctionInfo, +SSARegMap, and a set of live in and live out registers for the function. See +MachineFunction.h for more information. +
+ +This section documents the phases described in the high-level design of the code generator. It +href="#high-level-design">high-level design of the code generator. It explains how they work and some of the rationale behind their design.
To Be Written
For the JIT or .o file writer
+