From 32467012f6db74b0c37f8181ac7c18092b3ad243 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Thu, 15 Jan 2015 00:15:30 +0000 Subject: [PATCH] [Hexagon] Replacing old versions of stores and loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226065 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonInstrInfo.cpp | 17 ------- lib/Target/Hexagon/HexagonInstrInfo.td | 20 ++++++++ lib/Target/Hexagon/HexagonInstrInfoV5.td | 57 ++-------------------- lib/Target/Hexagon/HexagonRegisterInfo.cpp | 7 +-- 4 files changed, 26 insertions(+), 75 deletions(-) diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 1f475ce06e2..d61b9353b9c 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -770,14 +770,6 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { return !invertPredicate ? Hexagon::C2_ccombinewt : Hexagon::C2_ccombinewf; - // Word. - case Hexagon::STriw_f: - return !invertPredicate ? Hexagon::S2_pstorerit_io: - Hexagon::S2_pstorerif_io; - case Hexagon::STriw_indexed_f: - return !invertPredicate ? Hexagon::S2_pstorerit_io: - Hexagon::S2_pstorerif_io; - // DEALLOC_RETURN. case Hexagon::L4_return: return !invertPredicate ? Hexagon::L4_return_t: @@ -1094,15 +1086,12 @@ isValidOffset(const int Opcode, const int Offset) const { switch(Opcode) { case Hexagon::L2_loadri_io: - case Hexagon::LDriw_f: case Hexagon::S2_storeri_io: - case Hexagon::STriw_f: return (Offset >= Hexagon_MEMW_OFFSET_MIN) && (Offset <= Hexagon_MEMW_OFFSET_MAX); case Hexagon::L2_loadrd_io: case Hexagon::S2_storerd_io: - case Hexagon::STrid_f: return (Offset >= Hexagon_MEMD_OFFSET_MIN) && (Offset <= Hexagon_MEMD_OFFSET_MAX); @@ -1550,12 +1539,6 @@ int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const { case Hexagon::STrih_shl_V4: return Hexagon::STrih_shl_nv_V4; - case Hexagon::STriw_f: - return Hexagon::S2_storerinew_io; - - case Hexagon::STriw_indexed_f: - return Hexagon::S4_storerinew_rr; - case Hexagon::STriw_shl_V4: return Hexagon::STriw_shl_nv_V4; diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index dc56f39240d..c66a4b12035 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -2774,6 +2774,26 @@ defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>; let accessSize = HalfWordAccess, isNVStorable = 0, isCodeGenOnly = 0 in defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>; +// Patterns for generating stores, where the address takes different forms: +// - frameindex,, +// - base + offset, +// - simple (base address without offset). +// These would usually be used together (via Storex_pat defined below), but +// in some cases one may want to apply different properties (such as +// AddedComplexity) to the individual patterns. +class Storex_fi_pat + : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; +class Storex_add_pat + : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)), + (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; + +multiclass Storex_pat { + def: Storex_fi_pat ; + def: Storex_add_pat ; +} + def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2, s4_3ImmPred:$offset), (S2_storerb_pi IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>; diff --git a/lib/Target/Hexagon/HexagonInstrInfoV5.td b/lib/Target/Hexagon/HexagonInstrInfoV5.td index ea565a6b23c..b0c4305d491 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV5.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV5.td @@ -112,8 +112,12 @@ def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss), let Inst{20-16} = Rss; } +defm: Loadx_pat; defm: Loadx_pat; +defm: Storex_pat; +defm: Storex_pat; + let isFP = 1, hasNewValue = 1, opNewValue = 0 in class T_MInstFloat MajOp, bits<3> MinOp> : MInst<(outs IntRegs:$Rd), @@ -485,59 +489,6 @@ def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>; def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>; } -let AddedComplexity = 20 in -def LDrid_indexed_f : LDInst<(outs DoubleRegs:$dst), - (ins IntRegs:$src1, s11_3Imm:$offset), - "$dst = memd($src1+#$offset)", - [(set DoubleRegs:$dst, (f64 (load (add IntRegs:$src1, - s11_3ImmPred:$offset))))]>, - Requires<[HasV5T]>; - -def LDriw_f : LDInst<(outs IntRegs:$dst), - (ins MEMri:$addr), "$dst = memw($addr)", - [(set IntRegs:$dst, (f32 (load ADDRriS11_2:$addr)))]>, - Requires<[HasV5T]>; - - -let AddedComplexity = 20 in -def LDriw_indexed_f : LDInst<(outs IntRegs:$dst), - (ins IntRegs:$src1, s11_2Imm:$offset), - "$dst = memw($src1+#$offset)", - [(set IntRegs:$dst, (f32 (load (add IntRegs:$src1, - s11_2ImmPred:$offset))))]>, - Requires<[HasV5T]>; - -// Store. -def STriw_f : STInst<(outs), - (ins MEMri:$addr, IntRegs:$src1), - "memw($addr) = $src1", - [(store (f32 IntRegs:$src1), ADDRriS11_2:$addr)]>, - Requires<[HasV5T]>; - -let AddedComplexity = 10 in -def STriw_indexed_f : STInst<(outs), - (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3), - "memw($src1+#$src2) = $src3", - [(store (f32 IntRegs:$src3), - (add IntRegs:$src1, s11_2ImmPred:$src2))]>, - Requires<[HasV5T]>; - -def STrid_f : STInst<(outs), - (ins MEMri:$addr, DoubleRegs:$src1), - "memd($addr) = $src1", - [(store (f64 DoubleRegs:$src1), ADDRriS11_2:$addr)]>, - Requires<[HasV5T]>; - -// Indexed store double word. -let AddedComplexity = 10 in -def STrid_indexed_f : STInst<(outs), - (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3), - "memd($src1+#$src2) = $src3", - [(store (f64 DoubleRegs:$src3), - (add IntRegs:$src1, s11_3ImmPred:$src2))]>, - Requires<[HasV5T]>; - - // Add let isCommutable = 1 in def fADD_rr : ALU64_rr<(outs IntRegs:$dst), diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp index fea5a8e56ad..8e016e4e1d2 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -164,8 +164,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, (MI.getOpcode() == Hexagon::L2_loadrh_io) || (MI.getOpcode() == Hexagon::L2_loadruh_io) || (MI.getOpcode() == Hexagon::L2_loadrb_io) || - (MI.getOpcode() == Hexagon::L2_loadrub_io) || - (MI.getOpcode() == Hexagon::LDriw_f)) { + (MI.getOpcode() == Hexagon::L2_loadrub_io)) { unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ? getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) : MI.getOperand(0).getReg(); @@ -188,9 +187,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } else if ((MI.getOpcode() == Hexagon::S2_storeri_io) || (MI.getOpcode() == Hexagon::S2_storerd_io) || (MI.getOpcode() == Hexagon::S2_storerh_io) || - (MI.getOpcode() == Hexagon::S2_storerb_io) || - (MI.getOpcode() == Hexagon::STrid_f) || - (MI.getOpcode() == Hexagon::STriw_f)) { + (MI.getOpcode() == Hexagon::S2_storerb_io)) { // For stores, we need a reserved register. Change // memw(r30 + #10000) = r0 to: // -- 2.34.1