From 2d8f6fe610fa859370c38cfbe38ff809a3a417de Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Thu, 21 Oct 2010 00:01:47 +0000 Subject: [PATCH] Custom lower f64 args passed in integer registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116977 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMFastISel.cpp | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index e500458cf18..4f0411d19a4 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -1356,6 +1356,21 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl &Args, VA.getLocReg()) .addReg(Arg); RegArgs.push_back(VA.getLocReg()); + } else if (VA.needsCustom()) { + // TODO: We need custom lowering for vector (v2f64) args. + if (VA.getLocVT() != MVT::f64) return false; + + CCValAssign &NextVA = ArgLocs[++i]; + + // TODO: Only handle register args for now. + if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false; + + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::VMOVRRD), VA.getLocReg()) + .addReg(NextVA.getLocReg(), RegState::Define) + .addReg(Arg)); + RegArgs.push_back(VA.getLocReg()); + RegArgs.push_back(NextVA.getLocReg()); } else { // Need to store return false; -- 2.34.1