From 29e9daa75019e6ee7b3305f7ef11a2cd85b96b55 Mon Sep 17 00:00:00 2001
From: Bruno Cardoso Lopes <bruno.cardoso@gmail.com>
Date: Tue, 20 Jul 2010 07:58:51 +0000
Subject: [PATCH] Fix Mips PR7473. Patch by stetorvs@gmail.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108816 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Mips/MipsISelLowering.cpp   |  6 +++---
 test/CodeGen/Mips/2010-07-20-Select.ll | 21 +++++++++++++++++++++
 2 files changed, 24 insertions(+), 3 deletions(-)
 create mode 100644 test/CodeGen/Mips/2010-07-20-Select.ll

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index b6ff2c371d5..f67572e8041 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -317,13 +317,13 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
     BB->addSuccessor(sinkMBB);
 
     //  sinkMBB:
-    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
+    //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
     //  ...
     BB = sinkMBB;
     BuildMI(*BB, BB->begin(), dl,
             TII->get(Mips::PHI), MI->getOperand(0).getReg())
-      .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
-      .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
+      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
+      .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
 
     MI->eraseFromParent();   // The pseudo instruction is gone now.
     return BB;
diff --git a/test/CodeGen/Mips/2010-07-20-Select.ll b/test/CodeGen/Mips/2010-07-20-Select.ll
new file mode 100644
index 00000000000..8b7f9a91937
--- /dev/null
+++ b/test/CodeGen/Mips/2010-07-20-Select.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s
+; Fix PR7473
+
+define i32 @main() nounwind readnone {
+entry:
+  %a = alloca i32, align 4                        ; <i32*> [#uses=2]
+  %c = alloca i32, align 4                        ; <i32*> [#uses=2]
+  volatile store i32 1, i32* %a, align 4
+  volatile store i32 0, i32* %c, align 4
+  %0 = volatile load i32* %a, align 4             ; <i32> [#uses=1]
+  %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
+; CHECK: addiu $4, $zero, 3
+  %iftmp.0.0 = select i1 %1, i32 3, i32 0         ; <i32> [#uses=1]
+  %2 = volatile load i32* %c, align 4             ; <i32> [#uses=1]
+  %3 = icmp eq i32 %2, 0                          ; <i1> [#uses=1]
+; CHECK: addu $4, $zero, $3
+; CHECK: addu $2, $5, $4
+  %iftmp.2.0 = select i1 %3, i32 0, i32 5         ; <i32> [#uses=1]
+  %4 = add nsw i32 %iftmp.2.0, %iftmp.0.0         ; <i32> [#uses=1]
+  ret i32 %4
+}
-- 
2.34.1