From 29e7485cda055417fbe97d8a434117a9913d0e3e Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 10 Mar 2015 16:16:49 +0000 Subject: [PATCH] R600/SI: Re-order MUBUF operands to match asm strings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231797 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstrInfo.cpp | 7 +++---- lib/Target/R600/SIInstrInfo.td | 16 ++++++++-------- lib/Target/R600/SIInstructions.td | 16 ++++++++-------- 3 files changed, 19 insertions(+), 20 deletions(-) diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index bcd5da18563..8ed4efe50b3 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -1863,10 +1863,10 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { MachineInstr *Addr64 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode)) .addOperand(*VData) - .addOperand(*SRsrc) .addReg(AMDGPU::NoRegister) // Dummy value for vaddr. // This will be replaced later // with the new value of vaddr. + .addOperand(*SRsrc) .addOperand(*SOffset) .addOperand(*Offset) .addImm(0) // glc @@ -2051,11 +2051,10 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con .addImm(AMDGPU::sub3); MI->setDesc(get(NewOpcode)); if (MI->getOperand(2).isReg()) { - MI->getOperand(2).setReg(MI->getOperand(1).getReg()); + MI->getOperand(2).setReg(SRsrc); } else { - MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false); + MI->getOperand(2).ChangeToRegister(SRsrc, false); } - MI->getOperand(1).setReg(SRsrc); MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset)); MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // glc diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 8bb5f30bb68..d765515a123 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -1911,7 +1911,7 @@ multiclass MUBUF_Load_Helper ; @@ -1919,7 +1919,7 @@ multiclass MUBUF_Load_Helper ; @@ -1927,14 +1927,14 @@ multiclass MUBUF_Load_Helper ; } let offen = 0, idxen = 0 in { defm _ADDR64 : MUBUFAddr64_m { let mayLoad = 0, mayStore = 1 in { defm : MUBUF_m ; /* int_SI_export */ @@ -2812,7 +2812,7 @@ def : Ext32Pat ; // Offset in an 32Bit VGPR def : Pat < (SIload_constant v4i32:$sbase, i32:$voff), - (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0, 0) + (BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, 0, 0, 0, 0, 0) >; // The multiplication scales from [0,1] to the unsigned integer range @@ -2974,7 +2974,7 @@ multiclass MUBUFLoad_Pattern ; } @@ -2991,7 +2991,7 @@ defm : MUBUFLoad_Pattern ; class MUBUFScratchLoadPat : Pat < (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset, u16imm:$offset))), - (Instr $srsrc, $vaddr, $soffset, $offset, 0, 0, 0) + (Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) >; def : MUBUFScratchLoadPat ; @@ -3018,7 +3018,7 @@ multiclass MUBUF_Load_Dword ; @@ -3026,7 +3026,7 @@ multiclass MUBUF_Load_Dword ; @@ -3034,7 +3034,7 @@ multiclass MUBUF_Load_Dword ; } @@ -3049,7 +3049,7 @@ defm : MUBUF_Load_Dword : Pat < (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset, u16imm:$offset)), - (Instr $value, $srsrc, $vaddr, $soffset, $offset, 0, 0, 0) + (Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) >; def : MUBUFScratchStorePat ; -- 2.34.1