From 296c1761416df3eb706dbcf5319f1f2267e1b4f7 Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Sun, 14 Oct 2007 01:58:32 +0000 Subject: [PATCH] Fix type mismatch error in PPC Altivec (only causes a problem when asserts are on). From vecLib. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42959 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index bd43d497d2d..9ef8f0ebc0d 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2570,14 +2570,14 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { if (SextVal >= 0 && SextVal <= 31) { SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); - LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS); + LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); } // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). if (SextVal >= -31 && SextVal <= 0) { SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); - LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS); + LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); } } -- 2.34.1