From 28d08fdb9f6572cafd5aae95c7caffa3cd136d8e Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Thu, 28 Feb 2008 22:31:51 +0000 Subject: [PATCH] Interface of getByValTypeAlignment differed between generic & x86 versions; change generic to follow x86 and improve comments. Add PPC version (not right for non-Darwin.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47734 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetLowering.h | 3 ++- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 5 +++-- lib/Target/PowerPC/PPCISelLowering.cpp | 11 +++++++++++ lib/Target/PowerPC/PPCISelLowering.h | 5 +++++ 4 files changed, 21 insertions(+), 3 deletions(-) diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 4f04ce34fc6..a3d24cc7b42 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -420,7 +420,8 @@ public: } /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate - /// function arguments in the caller parameter area. + /// function arguments in the caller parameter area. This is the actual + /// alignment, not its logarithm. virtual unsigned getByValTypeAlignment(const Type *Ty) const; /// getRegisterType - Return the type of registers that this ValueType will diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index ff5289e0882..61a155e978c 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -424,9 +424,10 @@ unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, } /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate -/// function arguments in the caller parameter area. +/// function arguments in the caller parameter area. This is the actual +/// alignment, not its logarithm. unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { - return Log2_32(TD->getCallFrameTypeAlignment(Ty)); + return TD->getCallFrameTypeAlignment(Ty); } SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table, diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 5500e37aaec..675c96a9b9f 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -351,6 +351,17 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) computeRegisterProperties(); } +/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate +/// function arguments in the caller parameter area. +unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { + TargetMachine &TM = getTargetMachine(); + // Darwin passes everything on 4 byte boundary. + if (TM.getSubtarget().isDarwin()) + return 4; + // FIXME Elf TBD + return 4; +} + const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (Opcode) { default: return 0; diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 3843998b508..9c539584a1f 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -268,6 +268,11 @@ namespace llvm { getRegForInlineAsmConstraint(const std::string &Constraint, MVT::ValueType VT) const; + /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate + /// function arguments in the caller parameter area. This is the actual + /// alignment, not its logarithm. + unsigned getByValTypeAlignment(const Type *Ty) const; + /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. virtual void LowerAsmOperandForConstraint(SDOperand Op, -- 2.34.1