From 24b34f8f3e301cce56be80dfa9a28a3dc8e0270a Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 22 Dec 2009 23:54:44 +0000 Subject: [PATCH] Add a SPR register class to the ARM target. Certain Thumb instructions require only SP (e.g. tSTRspi). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91944 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 2 +- lib/Target/ARM/ARMRegisterInfo.td | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index c92dd0e28ff..34d7d8f6eff 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -113,7 +113,7 @@ def t_addrmode_s1 : Operand, def t_addrmode_sp : Operand, ComplexPattern { let PrintMethod = "printThumbAddrModeSPOperand"; - let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); + let MIOperandInfo = (ops JustSP:$base, i32imm:$offsimm); } //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index d393e8d7e3e..9fbde815cdb 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -367,6 +367,19 @@ def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], // Condition code registers. def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; +// Just the stack pointer (for tSTRspi and friends). +def JustSP : RegisterClass<"ARM", [i32], 32, [SP]> { + let MethodProtos = [{ + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + JustSPClass::iterator + JustSPClass::allocation_order_end(const MachineFunction &MF) const { + return allocation_order_begin(MF); + } + }]; +} + //===----------------------------------------------------------------------===// // Subregister Set Definitions... now that we have all of the pieces, define the // sub registers for each register. -- 2.34.1