From 22fee2dff4c43b551aefa44a96ca74fcade6bfac Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 28 Jun 2011 20:07:07 +0000 Subject: [PATCH] Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8 --- Makefile.rules | 22 +--------- include/llvm/MC/MCInstrDesc.h | 2 +- lib/Target/ARM/ARMBaseInfo.h | 3 +- lib/Target/ARM/ARMBaseInstrInfo.cpp | 5 ++- lib/Target/ARM/ARMInstrInfo.cpp | 1 - lib/Target/ARM/CMakeLists.txt | 3 +- .../ARM/Disassembler/ARMDisassemblerCore.cpp | 1 + lib/Target/ARM/Makefile | 3 +- lib/Target/ARM/Thumb1InstrInfo.cpp | 1 - lib/Target/ARM/Thumb2InstrInfo.cpp | 1 - lib/Target/Alpha/Alpha.h | 3 +- lib/Target/Alpha/AlphaInstrInfo.cpp | 4 +- lib/Target/Alpha/CMakeLists.txt | 3 +- lib/Target/Alpha/Makefile | 3 +- lib/Target/Blackfin/Blackfin.h | 3 +- lib/Target/Blackfin/BlackfinInstrInfo.cpp | 2 + lib/Target/Blackfin/CMakeLists.txt | 3 +- lib/Target/Blackfin/Makefile | 4 +- lib/Target/CellSPU/CMakeLists.txt | 3 +- lib/Target/CellSPU/Makefile | 4 +- lib/Target/CellSPU/SPU.h | 3 +- lib/Target/CellSPU/SPUInstrInfo.cpp | 4 +- lib/Target/MBlaze/CMakeLists.txt | 3 +- .../Disassembler/MBlazeDisassembler.cpp | 1 + lib/Target/MBlaze/MBlaze.h | 3 +- lib/Target/MBlaze/MBlazeInstrInfo.cpp | 2 + lib/Target/MBlaze/Makefile | 4 +- lib/Target/MSP430/CMakeLists.txt | 3 +- lib/Target/MSP430/MSP430.h | 3 +- lib/Target/MSP430/MSP430InstrInfo.cpp | 4 +- lib/Target/MSP430/Makefile | 4 +- lib/Target/Mips/CMakeLists.txt | 3 +- lib/Target/Mips/Makefile | 4 +- lib/Target/Mips/Mips.h | 3 +- lib/Target/Mips/MipsInstrInfo.cpp | 2 + lib/Target/PTX/CMakeLists.txt | 3 +- lib/Target/PTX/Makefile | 1 - lib/Target/PTX/PTX.h | 3 +- lib/Target/PTX/PTXInstrInfo.cpp | 5 ++- lib/Target/PowerPC/CMakeLists.txt | 3 +- lib/Target/PowerPC/Makefile | 2 +- lib/Target/PowerPC/PPC.h | 3 +- lib/Target/PowerPC/PPCInstrInfo.cpp | 4 +- lib/Target/Sparc/CMakeLists.txt | 3 +- lib/Target/Sparc/Makefile | 4 +- lib/Target/Sparc/Sparc.h | 3 +- lib/Target/Sparc/SparcInstrInfo.cpp | 5 ++- lib/Target/SystemZ/CMakeLists.txt | 3 +- lib/Target/SystemZ/Makefile | 4 +- lib/Target/SystemZ/SystemZ.h | 3 +- lib/Target/SystemZ/SystemZInstrInfo.cpp | 5 ++- lib/Target/X86/CMakeLists.txt | 3 +- .../X86/InstPrinter/X86ATTInstPrinter.cpp | 4 +- .../X86/InstPrinter/X86InstComments.cpp | 2 +- .../X86/InstPrinter/X86IntelInstPrinter.cpp | 2 +- lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp | 5 +++ lib/Target/X86/MCTargetDesc/X86TargetDesc.h | 5 +++ lib/Target/X86/Makefile | 3 +- lib/Target/X86/X86.h | 7 +-- lib/Target/X86/X86InstrInfo.cpp | 4 +- lib/Target/XCore/CMakeLists.txt | 3 +- lib/Target/XCore/Makefile | 4 +- lib/Target/XCore/XCore.h | 3 +- lib/Target/XCore/XCoreInstrInfo.cpp | 4 +- utils/TableGen/InstrInfoEmitter.cpp | 43 +++++++++++++++++++ utils/TableGen/InstrInfoEmitter.h | 5 ++- utils/TableGen/TableGen.cpp | 14 +++--- 67 files changed, 165 insertions(+), 120 deletions(-) diff --git a/Makefile.rules b/Makefile.rules index 2acadd84003..46a3f1bdb90 100644 --- a/Makefile.rules +++ b/Makefile.rules @@ -1720,35 +1720,15 @@ TDFiles := $(strip $(wildcard $(PROJ_SRC_DIR)/*.td) \ # All of these files depend on tblgen and the .td files. $(INCTMPFiles) : $(TBLGEN) $(TDFiles) -$(TARGET:%=$(ObjDir)/%GenRegisterNames.inc.tmp): \ -$(ObjDir)/%GenRegisterNames.inc.tmp : %.td $(ObjDir)/.dir - $(Echo) "Building $( diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 6f48d967f91..adcbf1806fe 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -14,7 +14,6 @@ #include "ARMInstrInfo.h" #include "ARM.h" #include "ARMAddressingModes.h" -#include "ARMGenInstrInfo.inc" #include "ARMMachineFunctionInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/LiveVariables.h" diff --git a/lib/Target/ARM/CMakeLists.txt b/lib/Target/ARM/CMakeLists.txt index 0a0ed3c741b..b1d4f540247 100644 --- a/lib/Target/ARM/CMakeLists.txt +++ b/lib/Target/ARM/CMakeLists.txt @@ -1,8 +1,7 @@ set(LLVM_TARGET_DEFINITIONS ARM.td) tablegen(ARMGenRegisterInfo.inc -gen-register-info) -tablegen(ARMGenInstrNames.inc -gen-instr-enums) -tablegen(ARMGenInstrInfo.inc -gen-instr-desc) +tablegen(ARMGenInstrInfo.inc -gen-instr-info) tablegen(ARMGenCodeEmitter.inc -gen-emitter) tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter) tablegen(ARMGenAsmWriter.inc -gen-asm-writer) diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 851b2d0cf8c..fe165b04b43 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -71,6 +71,7 @@ /// { ARM::CCRRegClassID, 0|(1< EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. extern cl::opt EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. diff --git a/lib/Target/Sparc/CMakeLists.txt b/lib/Target/Sparc/CMakeLists.txt index 1a5b036c7ff..f3c691f5264 100644 --- a/lib/Target/Sparc/CMakeLists.txt +++ b/lib/Target/Sparc/CMakeLists.txt @@ -1,8 +1,7 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td) tablegen(SparcGenRegisterInfo.inc -gen-register-info) -tablegen(SparcGenInstrNames.inc -gen-instr-enums) -tablegen(SparcGenInstrInfo.inc -gen-instr-desc) +tablegen(SparcGenInstrInfo.inc -gen-instr-info) tablegen(SparcGenAsmWriter.inc -gen-asm-writer) tablegen(SparcGenDAGISel.inc -gen-dag-isel) tablegen(SparcGenSubtarget.inc -gen-subtarget) diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile index 4ef15193461..c8741b525b5 100644 --- a/lib/Target/Sparc/Makefile +++ b/lib/Target/Sparc/Makefile @@ -12,8 +12,8 @@ LIBRARYNAME = LLVMSparcCodeGen TARGET = Sparc # Make sure that tblgen is run, first thing. -BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \ - SparcGenInstrInfo.inc SparcGenAsmWriter.inc \ +BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \ + SparcGenAsmWriter.inc \ SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc DIRS = TargetInfo diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index 0f03ca35988..d68535b6046 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -41,7 +41,8 @@ namespace llvm { // Defines symbolic names for the Sparc instructions. // -#include "SparcGenInstrNames.inc" +#define GET_INSTRINFO_ENUM +#include "SparcGenInstrInfo.inc" namespace llvm { diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index afa3c1f88f9..c323af8625d 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -19,8 +19,11 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Support/ErrorHandling.h" -#include "SparcGenInstrInfo.inc" #include "SparcMachineFunctionInfo.h" + +#define GET_INSTRINFO_MC_DESC +#include "SparcGenInstrInfo.inc" + using namespace llvm; SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt index 5adf5e31615..47c7a9fe6c6 100644 --- a/lib/Target/SystemZ/CMakeLists.txt +++ b/lib/Target/SystemZ/CMakeLists.txt @@ -1,8 +1,7 @@ set(LLVM_TARGET_DEFINITIONS SystemZ.td) tablegen(SystemZGenRegisterInfo.inc -gen-register-info) -tablegen(SystemZGenInstrNames.inc -gen-instr-enums) -tablegen(SystemZGenInstrInfo.inc -gen-instr-desc) +tablegen(SystemZGenInstrInfo.inc -gen-instr-info) tablegen(SystemZGenAsmWriter.inc -gen-asm-writer) tablegen(SystemZGenDAGISel.inc -gen-dag-isel) tablegen(SystemZGenCallingConv.inc -gen-callingconv) diff --git a/lib/Target/SystemZ/Makefile b/lib/Target/SystemZ/Makefile index 4b45615bc4f..682f343046d 100644 --- a/lib/Target/SystemZ/Makefile +++ b/lib/Target/SystemZ/Makefile @@ -12,8 +12,8 @@ LIBRARYNAME = LLVMSystemZCodeGen TARGET = SystemZ # Make sure that tblgen is run, first thing. -BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \ - SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \ +BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrInfo.inc \ + SystemZGenAsmWriter.inc \ SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc DIRS = TargetInfo diff --git a/lib/Target/SystemZ/SystemZ.h b/lib/Target/SystemZ/SystemZ.h index 8bf9fc54e80..84d83c00d94 100644 --- a/lib/Target/SystemZ/SystemZ.h +++ b/lib/Target/SystemZ/SystemZ.h @@ -57,6 +57,7 @@ namespace llvm { #include "SystemZGenRegisterInfo.inc" // Defines symbolic names for the SystemZ instructions. -#include "SystemZGenInstrNames.inc" +#define GET_INSTRINFO_ENUM +#include "SystemZGenInstrInfo.inc" #endif diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index 9488defc0af..b70e075f750 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -16,13 +16,16 @@ #include "SystemZInstrInfo.h" #include "SystemZMachineFunctionInfo.h" #include "SystemZTargetMachine.h" -#include "SystemZGenInstrInfo.inc" #include "llvm/Function.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/ErrorHandling.h" + +#define GET_INSTRINFO_MC_DESC +#include "SystemZGenInstrInfo.inc" + using namespace llvm; SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) diff --git a/lib/Target/X86/CMakeLists.txt b/lib/Target/X86/CMakeLists.txt index 31d69af890a..50464e8e9e7 100644 --- a/lib/Target/X86/CMakeLists.txt +++ b/lib/Target/X86/CMakeLists.txt @@ -2,8 +2,7 @@ set(LLVM_TARGET_DEFINITIONS X86.td) tablegen(X86GenRegisterInfo.inc -gen-register-info) tablegen(X86GenDisassemblerTables.inc -gen-disassembler) -tablegen(X86GenInstrNames.inc -gen-instr-enums) -tablegen(X86GenInstrInfo.inc -gen-instr-desc) +tablegen(X86GenInstrInfo.inc -gen-instr-info) tablegen(X86GenAsmWriter.inc -gen-asm-writer) tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1) tablegen(X86GenAsmMatcher.inc -gen-asm-matcher) diff --git a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp index d01a6007f21..53738b131df 100644 --- a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp @@ -16,19 +16,17 @@ #include "X86ATTInstPrinter.h" #include "X86InstComments.h" #include "X86Subtarget.h" +#include "MCTargetDesc/X86TargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" #include "llvm/Support/FormattedStream.h" -#include "X86GenInstrNames.inc" #include using namespace llvm; // Include the auto-generated portion of the assembly writer. -#define GET_REGINFO_ENUM -#include "X86GenRegisterInfo.inc" #define GET_INSTRUCTION_NAME #define PRINT_ALIAS_INSTR #include "X86GenAsmWriter.inc" diff --git a/lib/Target/X86/InstPrinter/X86InstComments.cpp b/lib/Target/X86/InstPrinter/X86InstComments.cpp index c642acc3b9a..5461c83d4d4 100644 --- a/lib/Target/X86/InstPrinter/X86InstComments.cpp +++ b/lib/Target/X86/InstPrinter/X86InstComments.cpp @@ -13,7 +13,7 @@ //===----------------------------------------------------------------------===// #include "X86InstComments.h" -#include "X86GenInstrNames.inc" +#include "MCTargetDesc/X86TargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/Support/raw_ostream.h" #include "../Utils/X86ShuffleDecode.h" diff --git a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp index 5f581bab390..411d832f278 100644 --- a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp +++ b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp @@ -16,12 +16,12 @@ #include "X86IntelInstPrinter.h" #include "X86InstComments.h" #include "X86Subtarget.h" +#include "MCTargetDesc/X86TargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" -#include "X86GenInstrNames.inc" #include using namespace llvm; diff --git a/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp index 7aa77bdf6f8..77bfbb9e74c 100644 --- a/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp +++ b/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp @@ -12,11 +12,16 @@ //===----------------------------------------------------------------------===// #include "X86TargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" #define GET_REGINFO_MC_DESC #include "X86GenRegisterInfo.inc" + +#define GET_INSTRINFO_MC_DESC +#include "X86GenInstrInfo.inc" + using namespace llvm; MCRegisterInfo *createX86MCRegisterInfo() { diff --git a/lib/Target/X86/MCTargetDesc/X86TargetDesc.h b/lib/Target/X86/MCTargetDesc/X86TargetDesc.h index 0d876dc953c..9ab622d31d1 100644 --- a/lib/Target/X86/MCTargetDesc/X86TargetDesc.h +++ b/lib/Target/X86/MCTargetDesc/X86TargetDesc.h @@ -26,4 +26,9 @@ extern Target TheX86_32Target, TheX86_64Target; #define GET_REGINFO_ENUM #include "X86GenRegisterInfo.inc" +// Defines symbolic names for the X86 instructions. +// +#define GET_INSTRINFO_ENUM +#include "X86GenInstrInfo.inc" + #endif diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile index fad83438d06..25da36740fb 100644 --- a/lib/Target/X86/Makefile +++ b/lib/Target/X86/Makefile @@ -12,8 +12,7 @@ LIBRARYNAME = LLVMX86CodeGen TARGET = X86 # Make sure that tblgen is run, first thing. -BUILT_SOURCES = X86GenRegisterInfo.inc \ - X86GenInstrNames.inc X86GenInstrInfo.inc \ +BUILT_SOURCES = X86GenRegisterInfo.inc X86GenInstrInfo.inc \ X86GenAsmWriter.inc X86GenAsmMatcher.inc \ X86GenAsmWriter1.inc X86GenDAGISel.inc \ X86GenDisassemblerTables.inc X86GenFastISel.inc \ diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h index 896bf0a7dca..9d66c2f84f9 100644 --- a/lib/Target/X86/X86.h +++ b/lib/Target/X86/X86.h @@ -15,6 +15,7 @@ #ifndef TARGET_X86_H #define TARGET_X86_H +#include "MCTargetDesc/X86TargetDesc.h" #include "llvm/Support/DataTypes.h" #include "llvm/Target/TargetMachine.h" @@ -86,10 +87,4 @@ MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS, } // End llvm namespace -#include "MCTargetDesc/X86TargetDesc.h" - -// Defines symbolic names for the X86 instructions. -// -#include "X86GenInstrNames.inc" - #endif diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index f875010e04e..3112dc7382a 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -13,7 +13,6 @@ #include "X86InstrInfo.h" #include "X86.h" -#include "X86GenInstrInfo.inc" #include "X86InstrBuilder.h" #include "X86MachineFunctionInfo.h" #include "X86Subtarget.h" @@ -36,6 +35,9 @@ #include "llvm/MC/MCAsmInfo.h" #include +#define GET_INSTRINFO_MC_DESC +#include "X86GenInstrInfo.inc" + using namespace llvm; static cl::opt diff --git a/lib/Target/XCore/CMakeLists.txt b/lib/Target/XCore/CMakeLists.txt index f6e7c20c910..358141cab90 100644 --- a/lib/Target/XCore/CMakeLists.txt +++ b/lib/Target/XCore/CMakeLists.txt @@ -1,8 +1,7 @@ set(LLVM_TARGET_DEFINITIONS XCore.td) tablegen(XCoreGenRegisterInfo.inc -gen-register-info) -tablegen(XCoreGenInstrNames.inc -gen-instr-enums) -tablegen(XCoreGenInstrInfo.inc -gen-instr-desc) +tablegen(XCoreGenInstrInfo.inc -gen-instr-info) tablegen(XCoreGenAsmWriter.inc -gen-asm-writer) tablegen(XCoreGenDAGISel.inc -gen-dag-isel) tablegen(XCoreGenCallingConv.inc -gen-callingconv) diff --git a/lib/Target/XCore/Makefile b/lib/Target/XCore/Makefile index ddc85dd09c7..ec6fb4c6040 100644 --- a/lib/Target/XCore/Makefile +++ b/lib/Target/XCore/Makefile @@ -12,8 +12,8 @@ LIBRARYNAME = LLVMXCoreCodeGen TARGET = XCore # Make sure that tblgen is run, first thing. -BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \ - XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \ +BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \ + XCoreGenAsmWriter.inc \ XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ XCoreGenSubtarget.inc diff --git a/lib/Target/XCore/XCore.h b/lib/Target/XCore/XCore.h index 69c343dc2fb..ec4ab911281 100644 --- a/lib/Target/XCore/XCore.h +++ b/lib/Target/XCore/XCore.h @@ -37,6 +37,7 @@ namespace llvm { // Defines symbolic names for the XCore instructions. // -#include "XCoreGenInstrNames.inc" +#define GET_INSTRINFO_ENUM +#include "XCoreGenInstrInfo.inc" #endif diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 9cb6a7d17b5..97a1d52be86 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -18,11 +18,13 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" -#include "XCoreGenInstrInfo.inc" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#define GET_INSTRINFO_MC_DESC +#include "XCoreGenInstrInfo.inc" + namespace llvm { namespace XCore { diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index fa2b19264d9..2f21ea6e399 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -156,9 +156,15 @@ void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, // run - Emit the main instruction description records for the target... void InstrInfoEmitter::run(raw_ostream &OS) { + emitEnums(OS); + GatherItinClasses(); EmitSourceFileHeader("Target Instruction Descriptors", OS); + + OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n"; + OS << "#undef GET_INSTRINFO_MC_DESC\n"; + OS << "namespace llvm {\n\n"; CodeGenTarget &Target = CDP.getTargetInfo(); @@ -202,6 +208,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) { OperandInfoIDs, OS); OS << "};\n"; OS << "} // End llvm namespace \n"; + + OS << "#endif // GET_INSTRINFO_MC_DESC\n\n"; } void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, @@ -283,3 +291,38 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; } + +// emitEnums - Print out enum values for all of the instructions. +void InstrInfoEmitter::emitEnums(raw_ostream &OS) { + EmitSourceFileHeader("Target Instruction Enum Values", OS); + + OS << "\n#ifdef GET_INSTRINFO_ENUM\n"; + OS << "#undef GET_INSTRINFO_ENUM\n"; + + OS << "namespace llvm {\n\n"; + + CodeGenTarget Target(Records); + + // We must emit the PHI opcode first... + std::string Namespace = Target.getInstNamespace(); + + if (Namespace.empty()) { + fprintf(stderr, "No instructions defined!\n"); + exit(1); + } + + const std::vector &NumberedInstructions = + Target.getInstructionsByEnumValue(); + + OS << "namespace " << Namespace << " {\n"; + OS << " enum {\n"; + for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + OS << " " << NumberedInstructions[i]->TheDef->getName() + << "\t= " << i << ",\n"; + } + OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n"; + OS << " };\n}\n"; + OS << "} // End llvm namespace \n"; + + OS << "#endif // GET_INSTRINFO_ENUM\n\n"; +} diff --git a/utils/TableGen/InstrInfoEmitter.h b/utils/TableGen/InstrInfoEmitter.h index a665d40ecb1..165ce423ab6 100644 --- a/utils/TableGen/InstrInfoEmitter.h +++ b/utils/TableGen/InstrInfoEmitter.h @@ -39,8 +39,9 @@ public: void run(raw_ostream &OS); private: - typedef std::map, unsigned> OperandInfoMapTy; - + void emitEnums(raw_ostream &OS); + + typedef std::map, unsigned> OperandInfoMapTy; void emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map, unsigned> &EL, diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp index 6f220c92c68..ce16c9ade8e 100644 --- a/utils/TableGen/TableGen.cpp +++ b/utils/TableGen/TableGen.cpp @@ -28,7 +28,6 @@ #include "EDEmitter.h" #include "Error.h" #include "FastISelEmitter.h" -#include "InstrEnumEmitter.h" #include "InstrInfoEmitter.h" #include "IntrinsicEmitter.h" #include "LLVMCConfigurationEmitter.h" @@ -55,7 +54,9 @@ enum ActionType { PrintRecords, GenEmitter, GenRegisterInfo, - GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher, + GenInstrInfo, + GenAsmWriter, + GenAsmMatcher, GenARMDecoder, GenDisassembler, GenCallingConv, @@ -95,9 +96,7 @@ namespace { "Generate machine code emitter"), clEnumValN(GenRegisterInfo, "gen-register-info", "Generate registers and register classes info"), - clEnumValN(GenInstrEnums, "gen-instr-enums", - "Generate enum values for instructions"), - clEnumValN(GenInstrs, "gen-instr-desc", + clEnumValN(GenInstrInfo, "gen-instr-info", "Generate instruction descriptions"), clEnumValN(GenCallingConv, "gen-callingconv", "Generate calling convention descriptions"), @@ -260,10 +259,7 @@ int main(int argc, char **argv) { case GenRegisterInfo: RegisterInfoEmitter(Records).run(Out.os()); break; - case GenInstrEnums: - InstrEnumEmitter(Records).run(Out.os()); - break; - case GenInstrs: + case GenInstrInfo: InstrInfoEmitter(Records).run(Out.os()); break; case GenCallingConv: -- 2.34.1