From 22266c1d4817fc30355a90bb264ede08482bba3a Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Wed, 28 Aug 2013 14:39:19 +0000 Subject: [PATCH] ARM: Use "dmb sy" for barriers on M-class CPUs The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction on v6M or v7M (well, it does the same thing but software is strongly discouraged from using it) so we should emit a full-system barrier there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189483 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 5 ++++- test/CodeGen/Thumb/barrier.ll | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 74353c1788a..063f1d46c7d 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -2600,7 +2600,10 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, ConstantSDNode *OrdN = cast(Op.getOperand(1)); AtomicOrdering Ord = static_cast(OrdN->getZExtValue()); unsigned Domain = ARM_MB::ISH; - if (Subtarget->isSwift() && Ord == Release) { + if (Subtarget->isMClass()) { + // Only a full system barrier exists in the M-class architectures. + Domain = ARM_MB::SY; + } else if (Subtarget->isSwift() && Ord == Release) { // Swift happens to implement ISHST barriers in a way that's compatible with // Release semantics but weaker than ISH so we'd be fools not to use // it. Beware: other processors probably don't! diff --git a/test/CodeGen/Thumb/barrier.ll b/test/CodeGen/Thumb/barrier.ll index 8fca273cc23..1c27fa09884 100644 --- a/test/CodeGen/Thumb/barrier.ll +++ b/test/CodeGen/Thumb/barrier.ll @@ -7,7 +7,7 @@ define void @t1() { ; V6: blx {{_*}}sync_synchronize ; V6M-LABEL: t1: -; V6M: dmb ish +; V6M: dmb sy fence seq_cst ret void } -- 2.34.1