From 1f2d4d356d9ad1fa351f532949d6dfcda83e4457 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 20 Oct 2015 19:04:53 +0000 Subject: [PATCH] [Hexagon] Remove the remnants of isConstExtProfitable git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250845 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/Hexagon.td | 2 +- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 14 --- lib/Target/Hexagon/HexagonInstrFormats.td | 1 - lib/Target/Hexagon/HexagonInstrInfo.td | 4 +- lib/Target/Hexagon/HexagonInstrInfoV4.td | 2 +- lib/Target/Hexagon/HexagonIntrinsics.td | 22 ++--- lib/Target/Hexagon/HexagonOperands.td | 107 +++------------------ 7 files changed, 27 insertions(+), 125 deletions(-) diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index d30f92ea4c4..ca283ed8f34 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -161,7 +161,7 @@ def getNonNVStore : InstrMapping { def getBasedWithImmOffset : InstrMapping { let FilterClass = "AddrModeRel"; let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", - "isMEMri", "isFloat"]; + "isFloat"]; let ColFields = ["addrMode"]; let KeyCol = ["Absolute"]; let ValueCols = [["BaseImmOffset"]]; diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index aa68c11a6b0..c453552ffae 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -104,7 +104,6 @@ public: SDNode *SelectConstantFP(SDNode *N); SDNode *SelectAdd(SDNode *N); SDNode *SelectBitOp(SDNode *N); - bool isConstExtProfitable(SDNode *N) const; // XformMskToBitPosU5Imm - Returns the bit position which // the single bit 32 bit mask represents. @@ -1328,19 +1327,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, return false; } -bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const { - unsigned UseCount = 0; - unsigned CallCount = 0; - for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { - // Ignore call instructions. - if (I->getOpcode() == ISD::CopyToReg) - ++CallCount; - UseCount++; - } - - return (UseCount <= 1) || (CallCount > 1); - -} void HexagonDAGToDAGISel::PreprocessISelDAG() { SelectionDAG &DAG = *CurDAG; diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index c47741cca60..3c5ec1701dc 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -188,7 +188,6 @@ class InstHexagon pattern, string PNewValue = ""; string NValueST = ""; // Set to "true" for new-value stores. string InputType = ""; // Input is "imm" or "reg" type. - string isMEMri = "false"; // Set to "true" for load/store with MEMri operand. string isFloat = "false"; // Set to "true" for the floating-point load/store. string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 37f3e531fcc..61c92dc3203 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -2825,7 +2825,7 @@ let CextOpcode = "ADD_acc" in { let isExtentSigned = 1 in def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext, [(set (i32 IntRegs:$dst), - (add (add (i32 IntRegs:$src2), s16_16ImmPred:$src3), + (add (add (i32 IntRegs:$src2), s32ImmPred:$src3), (i32 IntRegs:$src1)))]>, ImmRegRel; def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0, @@ -2859,7 +2859,7 @@ class T_MType_acc_pat2 def : T_MType_acc_pat2 ; def : T_MType_acc_pat1 ; -def : T_MType_acc_pat1 ; +def : T_MType_acc_pat1 ; def : T_MType_acc_pat2 ; //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 65b0f497436..4eee425e985 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -1903,7 +1903,7 @@ def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6), "$Rd = add($Rs, add($Ru, #$s6))" , [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), - (add (i32 IntRegs:$Ru), s16_16ImmPred:$s6)))], + (add (i32 IntRegs:$Ru), s32ImmPred:$s6)))], "", ALU64_tc_2_SLOT23> { bits<5> Rd; bits<5> Rs; diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td index 1d0d015f798..95159db0804 100644 --- a/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/lib/Target/Hexagon/HexagonIntrinsics.td @@ -691,15 +691,15 @@ def: T_RR_pat; def: T_RR_pat; def: T_RR_pat; -def: T_II_pat; +def: T_II_pat; def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs), (I32:$Rt))), (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>; // Mux -def : T_QRI_pat; -def : T_QIR_pat; -def : T_QII_pat; +def : T_QRI_pat; +def : T_QIR_pat; +def : T_QII_pat; // Shift halfword def : T_R_pat; @@ -720,17 +720,17 @@ def : T_RR_pat; def : T_RR_pat; def : T_RR_pat; -def : T_RI_pat; -def : T_RI_pat; -def : T_RI_pat; +def : T_RI_pat; +def : T_RI_pat; +def : T_RI_pat; -def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)), +def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s32ImmPred:$src2)), (i32 (C2_cmpgti (I32:$src1), - (DEC_CONST_SIGNED s8ExtPred:$src2)))>; + (DEC_CONST_SIGNED s32ImmPred:$src2)))>; -def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)), +def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u32ImmPred:$src2)), (i32 (C2_cmpgtui (I32:$src1), - (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>; + (DEC_CONST_UNSIGNED u32ImmPred:$src2)))>; // The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0. def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)), diff --git a/lib/Target/Hexagon/HexagonOperands.td b/lib/Target/Hexagon/HexagonOperands.td index 7e82c86fb3c..606511ec3bc 100644 --- a/lib/Target/Hexagon/HexagonOperands.td +++ b/lib/Target/Hexagon/HexagonOperands.td @@ -96,32 +96,12 @@ def s31_1ImmPred : PatLeaf<(i32 imm), [{ def s30_2ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<31,1>(v); + return isShiftedInt<30,2>(v); }]>; def s29_3ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<31,1>(v); -}]>; - -def s22_10ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<22,10>(v); -}]>; - -def s8_24ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<8,24>(v); -}]>; - -def s16_16ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<16,16>(v); -}]>; - -def s26_6ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<26,6>(v); + return isShiftedInt<29,3>(v); }]>; def s16ImmPred : PatLeaf<(i32 imm), [{ @@ -129,16 +109,6 @@ def s16ImmPred : PatLeaf<(i32 imm), [{ return isInt<16>(v); }]>; -def s13ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<13>(v); -}]>; - -def s12ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<12>(v); -}]>; - def s11_0ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); return isInt<11>(v); @@ -164,16 +134,6 @@ def s10ImmPred : PatLeaf<(i32 imm), [{ return isInt<10>(v); }]>; -def s9ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<9>(v); -}]>; - -def m9ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<9>(v) && (v != -256); -}]>; - def s8ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); return isInt<8>(v); @@ -245,19 +205,19 @@ def u26_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<26,6>(v); }]>; -def u16ImmPred : PatLeaf<(i32 imm), [{ +def u16_0ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); return isUInt<16>(v); }]>; -def u16_s8ImmPred : PatLeaf<(i32 imm), [{ +def u16_1ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); - return isShiftedUInt<16,8>(v); + return isShiftedUInt<16,1>(v); }]>; -def u16_0ImmPred : PatLeaf<(i32 imm), [{ +def u16_2ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); - return isUInt<16>(v); + return isShiftedUInt<16,2>(v); }]>; def u11_3ImmPred : PatLeaf<(i32 imm), [{ @@ -394,7 +354,7 @@ def Clr5ImmPred : PatLeaf<(i32 imm), [{ }]>; def SetClr5ImmPred : PatLeaf<(i32 imm), [{ - // SetClr5ImmPred predicate - True if the immediate is in range 0..31. + // True if the immediate is in range 0..31. int32_t v = (int32_t)N->getSExtValue(); return (v >= 0 && v <= 31); }]>; @@ -419,14 +379,13 @@ def Clr4ImmPred : PatLeaf<(i32 imm), [{ }]>; def SetClr4ImmPred : PatLeaf<(i32 imm), [{ - // SetClr4ImmPred predicate - True if the immediate is in the range 0..15. + // True if the immediate is in the range 0..15. int16_t v = (int16_t)N->getSExtValue(); return (v >= 0 && v <= 15); }]>; def Set3ImmPred : PatLeaf<(i32 imm), [{ - // Set3ImmPred predicate - True if the number is in the series of values: - // [ 2^0, 2^1, ... 2^7 ]. + // True if the number is in the series of values: [ 2^0, 2^1, ... 2^7 ]. // For use in setbit immediate. uint8_t v = (int8_t)N->getSExtValue(); // Constrain to 8 bits, and then check for single bit. @@ -434,9 +393,7 @@ def Set3ImmPred : PatLeaf<(i32 imm), [{ }]>; def Clr3ImmPred : PatLeaf<(i32 imm), [{ - // Clr3ImmPred predicate - True if the number is in the series of - // bit negated values: - // [ 2^0, 2^1, ... 2^7 ]. + // True if the number is in the series of bit negated values: [ 2^0, 2^1, ... 2^7 ]. // For use in setbit and clrbit immediate. uint8_t v = ~ (int8_t)N->getSExtValue(); // Constrain to 8 bits, and then check for single bit. @@ -444,7 +401,7 @@ def Clr3ImmPred : PatLeaf<(i32 imm), [{ }]>; def SetClr3ImmPred : PatLeaf<(i32 imm), [{ - // SetClr3ImmPred predicate - True if the immediate is in the range 0..7. + // True if the immediate is in the range 0..7. int8_t v = (int8_t)N->getSExtValue(); return (v >= 0 && v <= 7); }]>; @@ -476,46 +433,6 @@ let PrintMethod = "printExtOperand" in { def u6_3Ext : Operand; } -def s10ExtPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - if (isInt<10>(v)) - return true; - - // Return true if extending this immediate is profitable and the value - // can fit in a 32-bit signed field. - return isConstExtProfitable(Node) && isInt<32>(v); -}]>; - -def s8ExtPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - if (isInt<8>(v)) - return true; - - // Return true if extending this immediate is profitable and the value - // can fit in a 32-bit signed field. - return isConstExtProfitable(Node) && isInt<32>(v); -}]>; - -def u8ExtPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - if (isUInt<8>(v)) - return true; - - // Return true if extending this immediate is profitable and the value - // can fit in a 32-bit unsigned field. - return isConstExtProfitable(Node) && isUInt<32>(v); -}]>; - -def u9ExtPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - if (isUInt<9>(v)) - return true; - - // Return true if extending this immediate is profitable and the value - // can fit in a 32-bit unsigned field. - return isConstExtProfitable(Node) && isUInt<32>(v); -}]>; - def s4_7ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); -- 2.34.1