From 1b4cb8f061b3d6ed2f84ee4aaee993aa4d2b281d Mon Sep 17 00:00:00 2001 From: Rocky Hao Date: Fri, 24 Feb 2017 11:00:32 +0800 Subject: [PATCH] arm64: dts: rockchip: complete cpufreq config data for rk3328 Change-Id: I422ec388ab6d66e1ba669028d7b88525569e88d5 Signed-off-by: Rocky Hao --- arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 ++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts index 10a983c1ffdd..923786c23f87 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts @@ -77,6 +77,10 @@ }; }; +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + &emmc { bus-width = <8>; cap-mmc-highspeed; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 45d56914f7d3..af169ca376fa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -74,7 +74,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; -// clocks = <&cru ARMCLK>; + clocks = <&cru ARMCLK>; operating-points-v2 = <&cpu0_opp_table>; }; cpu1: cpu@1 { @@ -82,18 +82,21 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; }; }; -- 2.34.1