From 1a2cf3b4d9c6cac6123417aaa4aae3a9e4f7bb48 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Mon, 11 Oct 2010 19:02:04 +0000 Subject: [PATCH] Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116214 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 4 +++- test/CodeGen/X86/2010-10-08-cmpxchg8b.ll | 28 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/X86/2010-10-08-cmpxchg8b.ll diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index adf6fff3a61..1ab2f2b6c7b 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -8697,7 +8697,9 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, N->getOperand(1), swapInH.getValue(1) }; SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); + MachineMemOperand *MMO = cast(N)->getMemOperand(); + SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, + Ops, 3, T, MMO); SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, MVT::i32, Result.getValue(1)); SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, diff --git a/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll b/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll new file mode 100644 index 00000000000..0fd4a34862c --- /dev/null +++ b/test/CodeGen/X86/2010-10-08-cmpxchg8b.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin | FileCheck %s +; bug 8297 +; +; On i386, i64 cmpxchg is lowered during legalize types to extract the +; 64-bit result into a pair of fixed regs. So creation of the DAG node +; happens in a different place. See +; X86TargetLowering::ReplaceNodeResults, case ATOMIC_CMP_SWAP. +; +; Neither Atomic-xx.ll nor atomic_op.ll cover this. Those tests were +; autogenerated from C source before 64-bit variants were supported. +; +; Note that this case requires a loop around the cmpxchg to force +; machine licm to query alias anlysis, exposing a bad +; MachineMemOperand. +define void @foo(i64* %ptr) nounwind inlinehint { +entry: + br label %loop +loop: +; CHECK: lock +; CHECK-NEXT: cmpxchg8b + %r = call i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* %ptr, i64 0, i64 1) + %stored1 = icmp eq i64 %r, 0 + br i1 %stored1, label %loop, label %continue +continue: + ret void +} + +declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* nocapture, i64, i64) nounwind -- 2.34.1