From 18c2f13e0f9d0e5d6227cf6d1881e9ee3d1b6109 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 13 Jan 2005 20:50:02 +0000 Subject: [PATCH] Add new ImplicitDef node, rename CopyRegSDNode class to RegSDNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19535 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAG.h | 11 ++++++-- include/llvm/CodeGen/SelectionDAGNodes.h | 27 ++++++++++++------- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 12 ++++++--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 ++- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 5 ++-- .../SelectionDAG/SelectionDAGPrinter.cpp | 2 +- lib/Target/X86/X86ISelPattern.cpp | 4 +-- 7 files changed, 42 insertions(+), 22 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index ac6a9d72629..5b3fc05d08a 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -119,14 +119,21 @@ public: SDOperand getCopyToReg(SDOperand Chain, SDOperand N, unsigned Reg) { // Note: these are auto-CSE'd because the caller doesn't make requests that // could cause duplicates to occur. - SDNode *NN = new CopyRegSDNode(Chain, N, Reg); + SDNode *NN = new RegSDNode(Chain, N, Reg); AllNodes.push_back(NN); return SDOperand(NN, 0); } SDOperand getCopyFromReg(unsigned Reg, MVT::ValueType VT) { // Note: These nodes are auto-CSE'd by the caller of this method. - SDNode *NN = new CopyRegSDNode(Reg, VT); + SDNode *NN = new RegSDNode(ISD::CopyFromReg, Reg, VT); + AllNodes.push_back(NN); + return SDOperand(NN, 0); + } + + SDOperand getImplicitDef(unsigned Reg) { + // Note: These nodes are auto-CSE'd by the caller of this method. + SDNode *NN = new RegSDNode(ISD::ImplicitDef, Reg, MVT::Other); AllNodes.push_back(NN); return SDOperand(NN, 0); } diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 2957a51401c..be7acb5e361 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -58,16 +58,22 @@ namespace ISD { // CopyToReg - This node has chain and child nodes, and an associated // register number. The instruction selector must guarantee that the value - // of the value node is available in the register stored in the - // CopyRegSDNode object. + // of the value node is available in the register stored in the RegSDNode + // object. CopyToReg, // CopyFromReg - This node indicates that the input value is a virtual or // physical register that is defined outside of the scope of this - // SelectionDAG. The register number is available from the CopyRegSDNode - // object. + // SelectionDAG. The register is available from the RegSDNode object. CopyFromReg, + // ImplicitDef - This node indicates that the specified register is + // implicitly defined by some operation (e.g. its a live-in argument). This + // register is indicated in the RegSDNode object. The only operand to this + // is the token chain coming in, the only result is the token chain going + // out. + ImplicitDef, + // EXTRACT_ELEMENT - This is used to get the first or second (determined by // a Constant, which is required to be operand #1), element of the aggregate // value specified as operand #0. This is only for use before legalization, @@ -608,25 +614,26 @@ public: }; -class CopyRegSDNode : public SDNode { +class RegSDNode : public SDNode { unsigned Reg; protected: friend class SelectionDAG; - CopyRegSDNode(SDOperand Chain, SDOperand Src, unsigned reg) + RegSDNode(SDOperand Chain, SDOperand Src, unsigned reg) : SDNode(ISD::CopyToReg, Chain, Src), Reg(reg) { setValueTypes(MVT::Other); // Just a token chain. } - CopyRegSDNode(unsigned reg, MVT::ValueType VT) - : SDNode(ISD::CopyFromReg, VT), Reg(reg) { + RegSDNode(unsigned Opc, unsigned reg, MVT::ValueType VT) + : SDNode(Opc, VT), Reg(reg) { } public: unsigned getReg() const { return Reg; } - static bool classof(const CopyRegSDNode *) { return true; } + static bool classof(const RegSDNode *) { return true; } static bool classof(const SDNode *N) { return N->getOpcode() == ISD::CopyToReg || - N->getOpcode() == ISD::CopyFromReg; + N->getOpcode() == ISD::CopyFromReg || + N->getOpcode() == ISD::ImplicitDef; } }; diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 58f98894efe..c735faa3ace 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -244,6 +244,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { assert(getTypeAction(Node->getValueType(0)) == Legal && "This must be legal!"); break; + case ISD::ImplicitDef: + Tmp1 = LegalizeOp(Node->getOperand(0)); + if (Tmp1 != Node->getOperand(0)) + Result = DAG.getImplicitDef(cast(Node)->getReg()); + break; case ISD::Constant: // We know we don't need to expand constants here, constants only have one // value and we check that it is fine above. @@ -398,13 +403,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // Legalize the incoming value (must be legal). Tmp2 = LegalizeOp(Node->getOperand(1)); if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) - Result = DAG.getCopyToReg(Tmp1, Tmp2, - cast(Node)->getReg()); + Result = DAG.getCopyToReg(Tmp1, Tmp2, cast(Node)->getReg()); break; case Expand: { SDOperand Lo, Hi; ExpandOp(Node->getOperand(1), Lo, Hi); - unsigned Reg = cast(Node)->getReg(); + unsigned Reg = cast(Node)->getReg(); Result = DAG.getCopyToReg(Tmp1, Lo, Reg); Result = DAG.getCopyToReg(Result, Hi, Reg+1); assert(isTypeLegal(Result.getValueType()) && @@ -748,7 +752,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ } case ISD::CopyFromReg: { - unsigned Reg = cast(Node)->getReg(); + unsigned Reg = cast(Node)->getReg(); // Aggregate register values are always in consequtive pairs. Lo = DAG.getCopyFromReg(Reg, NVT); Hi = DAG.getCopyFromReg(Reg+1, NVT); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 2f5fdc37cd6..ecb9151e9e0 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -880,6 +880,7 @@ const char *SDNode::getOperationName() const { case ISD::ConstantPool: return "ConstantPoolIndex"; case ISD::CopyToReg: return "CopyToReg"; case ISD::CopyFromReg: return "CopyFromReg"; + case ISD::ImplicitDef: return "ImplicitDef"; case ISD::ADD: return "add"; case ISD::SUB: return "sub"; @@ -1006,7 +1007,7 @@ void SDNode::dump() const { if (LBB) std::cerr << LBB->getName() << " "; std::cerr << (const void*)BBDN->getBasicBlock() << ">"; - } else if (const CopyRegSDNode *C2V = dyn_cast(this)) { + } else if (const RegSDNode *C2V = dyn_cast(this)) { std::cerr << "getReg() << ">"; } else if (const ExternalSymbolSDNode *ES = dyn_cast(this)) { diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 6a81975292c..ed363e111c4 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -772,8 +772,9 @@ SDOperand SelectionDAGISel:: CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) { SelectionDAG &DAG = SDL.DAG; SDOperand Op = SDL.getValue(V); - if (CopyRegSDNode *CR = dyn_cast(Op)) - assert(CR->getReg() != Reg && "Copy from a reg to the same reg!"); + assert((Op.getOpcode() != ISD::CopyFromReg || + cast(Op)->getReg() != Reg) && + "Copy from a reg to the same reg!"); return DAG.getCopyToReg(DAG.getRoot(), Op, Reg); } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp index 49568ee2c37..f398568130d 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp @@ -85,7 +85,7 @@ std::string DOTGraphTraits::getNodeLabel(const SDNode *Node, if (LBB) Op += LBB->getName(); //Op += " " + (const void*)BBDN->getBasicBlock(); - } else if (const CopyRegSDNode *C2V = dyn_cast(Node)) { + } else if (const RegSDNode *C2V = dyn_cast(Node)) { Op += " #" + utostr(C2V->getReg()); } else if (const ExternalSymbolSDNode *ES = dyn_cast(Node)) { diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp index d13dbdf077f..89b90504abf 100644 --- a/lib/Target/X86/X86ISelPattern.cpp +++ b/lib/Target/X86/X86ISelPattern.cpp @@ -1023,7 +1023,7 @@ unsigned ISel::SelectExpr(SDOperand N) { if (Node->getOpcode() == ISD::CopyFromReg) // Just use the specified register as our input. - return dyn_cast(Node)->getReg(); + return dyn_cast(Node)->getReg(); unsigned &Reg = ExprMap[N]; if (Reg) return Reg; @@ -2111,7 +2111,7 @@ void ISel::Select(SDOperand N) { Tmp1 = SelectExpr(N.getOperand(1)); Select(N.getOperand(0)); } - Tmp2 = cast(N)->getReg(); + Tmp2 = cast(N)->getReg(); if (Tmp1 != Tmp2) { switch (N.getOperand(1).getValueType()) { -- 2.34.1