From 1867054643c20c3027421ab7711664b4d55fe4c6 Mon Sep 17 00:00:00 2001 From: Nate Begeman Date: Tue, 5 Apr 2005 22:36:56 +0000 Subject: [PATCH] Add MULHU and MULHS nodes for the high part of an (un)signed 32x32=64b multiply. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21102 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAGNodes.h | 2 +- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 568f66c9f63..cdb84eef472 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -90,7 +90,7 @@ namespace ISD { // Simple binary arithmetic operators. - ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, + ADD, SUB, MUL, MULHU, MULHS, SDIV, UDIV, SREM, UREM, // Bitwise operators. AND, OR, XOR, SHL, SRA, SRL, diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 105d39d1fa5..858b8ddab8e 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1130,6 +1130,8 @@ const char *SDNode::getOperationName() const { case ISD::ADD: return "add"; case ISD::SUB: return "sub"; case ISD::MUL: return "mul"; + case ISD::MULHU: return "mulhu"; + case ISD::MULHS: return "mulhs"; case ISD::SDIV: return "sdiv"; case ISD::UDIV: return "udiv"; case ISD::SREM: return "srem"; -- 2.34.1