From 177d87ac8d974529b07430b2088f699ed279cd1d Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Sat, 1 Dec 2012 01:22:44 +0000 Subject: [PATCH] misched: Fix the DAG builder to handle an undef operand at ExitSU. Assertion failed: (VNI && "No value to read by operand") rdar://12790267. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169071 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/ScheduleDAGInstrs.cpp | 3 ++- test/CodeGen/X86/misched-new.ll | 26 ++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index 2b00b596d3b..fd75576c786 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -210,7 +210,8 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() { Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1)); else { assert(!IsPostRA && "Virtual register encountered after regalloc."); - addVRegUseDeps(&ExitSU, i); + if (MO.readsReg()) // ignore undef operands + addVRegUseDeps(&ExitSU, i); } } } else { diff --git a/test/CodeGen/X86/misched-new.ll b/test/CodeGen/X86/misched-new.ll index cec04b534fb..a39ea03af55 100644 --- a/test/CodeGen/X86/misched-new.ll +++ b/test/CodeGen/X86/misched-new.ll @@ -51,3 +51,29 @@ if.end: ; preds = %if.then, %entry } declare void @bar(i32,i32) + +; Test that the DAG builder can handle an undef vreg on ExitSU. +; CHECK: hasundef +; CHECK: call + +%t0 = type { i32, i32, i8 } +%t6 = type { i32 (...)**, %t7* } +%t7 = type { i32 (...)** } + +define void @hasundef() unnamed_addr uwtable ssp align 2 { + %1 = alloca %t0, align 8 + br i1 undef, label %3, label %2 + +;