From 143931069630b2600a57feb0416c28cba12a7ba1 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 21 Jun 2016 15:18:00 +0800 Subject: [PATCH] clk: rockchip: rk3399: add 65M for PLL freq VPLL need 65M freq for some HDMI display. Change-Id: I4f07c97282fb48fc504b54a07838ccb0bbb0355a Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3399.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index b5a95d87888a..d60fcfea2d56 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -102,6 +102,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), + RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), { /* sentinel */ }, -- 2.34.1