From 12bd9f11c0bdd708a6f62bba7f83e2576f9ff328 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 5 Nov 2014 19:01:17 +0000 Subject: [PATCH] R600/SI: Remove SI_ADDR64_RSRC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221382 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 13 ++-- lib/Target/R600/SIISelLowering.cpp | 83 +++++++++++++++++--------- lib/Target/R600/SIISelLowering.h | 2 + lib/Target/R600/SIInstructions.td | 8 --- 4 files changed, 62 insertions(+), 44 deletions(-) diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp index 8a9340289d8..face98fe148 100644 --- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp +++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp @@ -850,11 +850,6 @@ bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base, return true; } -static SDValue wrapAddr64Rsrc(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) { - return SDValue(DAG->getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::v4i32, - Ptr), 0); -} - static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) { return isUInt<12>(Imm->getZExtValue()); } @@ -930,9 +925,14 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, ConstantSDNode *C = cast(Addr64); if (C->getSExtValue()) { SDLoc DL(Addr); - SRsrc = wrapAddr64Rsrc(CurDAG, DL, Ptr); + + const SITargetLowering& Lowering = + *static_cast(getTargetLowering()); + + SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); return true; } + return false; } @@ -951,7 +951,6 @@ static SDValue buildSMovImm32(SelectionDAG *DAG, SDLoc DL, uint64_t Val) { static SDValue buildRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) { - SDValue PtrLo = DAG->getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr); SDValue PtrHi = DAG->getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr); if (RsrcDword1) { diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index c2b60d190ec..b1788a2b1b3 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -606,37 +606,11 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( MachineBasicBlock::iterator I = *MI; const SIInstrInfo *TII = static_cast( getTargetMachine().getSubtargetImpl()->getInstrInfo()); - MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); switch (MI->getOpcode()) { default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); case AMDGPU::BRANCH: return BB; - case AMDGPU::SI_ADDR64_RSRC: { - unsigned SuperReg = MI->getOperand(0).getReg(); - unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass); - unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass); - unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); - unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo) - .addOperand(MI->getOperand(1)); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo) - .addImm(0); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi) - .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi) - .addReg(SubRegHiLo) - .addImm(AMDGPU::sub0) - .addReg(SubRegHiHi) - .addImm(AMDGPU::sub1); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg) - .addReg(SubRegLo) - .addImm(AMDGPU::sub0_sub1) - .addReg(SubRegHi) - .addImm(AMDGPU::sub2_sub3); - MI->eraseFromParent(); - break; - } case AMDGPU::V_SUB_F64: { unsigned DestReg = MI->getOperand(0).getReg(); BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg) @@ -1995,6 +1969,56 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, } } +static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) { + SDValue K = DAG.getTargetConstant(Val, MVT::i32); + return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0); +} + +MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG, + SDLoc DL, + SDValue Ptr) const { +#if 1 + // XXX - Workaround for moveToVALU not handling different register class + // inserts for REG_SEQUENCE. + + // Build the half of the subregister with the constants. + const SDValue Ops0[] = { + DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, MVT::i32), + buildSMovImm32(DAG, DL, 0), + DAG.getTargetConstant(AMDGPU::sub0, MVT::i32), + buildSMovImm32(DAG, DL, AMDGPU::RSRC_DATA_FORMAT >> 32), + DAG.getTargetConstant(AMDGPU::sub1, MVT::i32) + }; + + SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, + MVT::v2i32, Ops0), 0); + + // Combine the constants and the pointer. + const SDValue Ops1[] = { + DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32), + Ptr, + DAG.getTargetConstant(AMDGPU::sub0_sub1, MVT::i32), + SubRegHi, + DAG.getTargetConstant(AMDGPU::sub2_sub3, MVT::i32) + }; + + return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1); +#else + const SDValue Ops[] = { + DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32), + Ptr, + DAG.getTargetConstant(AMDGPU::sub0_sub1, MVT::i32), + buildSMovImm32(DAG, DL, 0), + DAG.getTargetConstant(AMDGPU::sub2, MVT::i32), + buildSMovImm32(DAG, DL, AMDGPU::RSRC_DATA_FORMAT >> 32), + DAG.getTargetConstant(AMDGPU::sub3, MVT::i32) + }; + + return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops); + +#endif +} + MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const { @@ -2020,9 +2044,10 @@ MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N, return N; } ConstantSDNode *Offset = cast(N->getOperand(1)); - MachineSDNode *RSrc = DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, - MVT::i128, - DAG.getConstant(0, MVT::i64)); + + const SDValue Zero64 = DAG.getTargetConstant(0, MVT::i64); + SDValue Ptr(DAG.getMachineNode(AMDGPU::S_MOV_B64, DL, MVT::i64, Zero64), 0); + MachineSDNode *RSrc = wrapAddr64Rsrc(DAG, DL, Ptr); SmallVector Ops; Ops.push_back(SDValue(RSrc, 0)); diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h index e9b7d4c565e..be8c951e6b9 100644 --- a/lib/Target/R600/SIISelLowering.h +++ b/lib/Target/R600/SIISelLowering.h @@ -105,6 +105,8 @@ public: SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const override; void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; + + MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const; }; } // End namespace llvm diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 01d2a9f3364..3842f8489ae 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1802,14 +1802,6 @@ def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST; let usesCustomInserter = 1 in { -// This pseudo instruction takes a pointer as input and outputs a resource -// constant that can be used with the ADDR64 MUBUF instructions. -def SI_ADDR64_RSRC : InstSI < - (outs SReg_128:$srsrc), - (ins SSrc_64:$ptr), - "", [] ->; - def V_SUB_F64 : InstSI < (outs VReg_64:$dst), (ins VReg_64:$src0, VReg_64:$src1), -- 2.34.1