From 124f7d9b257ad99c6a75e0293c949333c94218a1 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 19 Sep 2015 00:03:56 +0000 Subject: [PATCH] AMDGPU: Add failing testcase for live interval construction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248067 91177308-0d34-0410-b5e6-96231b3b80d8 --- ...partially-dead-super-register-immediate.ll | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll diff --git a/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll b/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll new file mode 100644 index 00000000000..760ac706dbd --- /dev/null +++ b/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll @@ -0,0 +1,29 @@ +; XFAIL: * +; RUN: llc -march=amdgcn -verify-machineinstrs -verify-coalescing < %s + +; The original and requires materializing a 64-bit immediate for +; s_and_b64. This is split into 2 x v_and_i32, part of the immediate +; is folded through the reg_sequence into the v_and_i32 operand, and +; only half of the result is ever used. +; +; During live interval construction, the first sub register def is +; incorrectly marked as dead. + +declare i32 @llvm.r600.read.tidig.x() #1 + +define void @dead_def_subregister(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) #0 { + %tid = call i32 @llvm.r600.read.tidig.x() #1 + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid + %val = load i64, i64 addrspace(1)* %in.gep + + %lshr = shl i64 %val, 24 + %and1 = and i64 %lshr, 2190433320969 ; (255 << 33) | 9 + %vec = bitcast i64 %and1 to <2 x i32> + %elt1 = extractelement <2 x i32> %vec, i32 1 + + store i32 %elt1, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } -- 2.34.1