From 0f8d9c04d9feef86cee35cf5fecfb348a6b3de50 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Tue, 13 Nov 2007 00:44:25 +0000 Subject: [PATCH] Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If not, then there is the potential for the stack to be changed while the stack's being used by another instruction (like a call). This can only result in tears... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAG.h | 14 +++++++++++++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 25 ++++++++++++++++++++++-- lib/Target/ARM/ARMISelLowering.cpp | 8 ++++---- lib/Target/ARM/ARMInstrInfo.td | 16 ++++++++------- lib/Target/ARM/ARMInstrThumb.td | 6 +++--- lib/Target/ARM/ARMRegisterInfo.cpp | 5 ++++- lib/Target/Alpha/AlphaISelLowering.cpp | 6 ++++-- lib/Target/Alpha/AlphaInstrInfo.td | 20 ++++++++++++------- lib/Target/IA64/IA64ISelLowering.cpp | 7 ++++--- lib/Target/Mips/MipsISelLowering.cpp | 10 ++++------ lib/Target/Mips/MipsInstrInfo.td | 17 +++++++++------- lib/Target/PowerPC/PPCISelLowering.cpp | 9 +++++++-- lib/Target/PowerPC/PPCInstrInfo.td | 15 +++++++------- lib/Target/Sparc/SparcISelDAGToDAG.cpp | 7 ++++--- lib/Target/Sparc/SparcInstrInfo.td | 17 +++++++++------- lib/Target/X86/X86ISelLowering.cpp | 14 ++++++------- lib/Target/X86/X86InstrInfo.td | 3 ++- 17 files changed, 129 insertions(+), 70 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 6a66d030345..b802debcc3f 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -275,6 +275,20 @@ public: return getNode(ISD::CALLSEQ_START, VTs, 2, Ops, 2); } + /// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a + /// flag result (to ensure it's not CSE'd). + SDOperand getCALLSEQ_END(SDOperand Chain, SDOperand Op1, SDOperand Op2, + SDOperand InFlag) { + SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag); + SmallVector Ops; + Ops.push_back(Chain); + Ops.push_back(Op1); + Ops.push_back(Op2); + Ops.push_back(InFlag); + return getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], + Ops.size() - (InFlag.Val == 0 ? 1 : 0)); + } + /// getNode - Gets or creates the specified node. /// SDOperand getNode(unsigned Opcode, MVT::ValueType VT); diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 4e096d8c163..5264141a056 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1142,12 +1142,20 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // The only option for this is to custom lower it. Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); assert(Tmp3.Val && "Target didn't custom lower this node!"); - assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && + + // The number of incoming and outgoing values should match; unless the final + // outgoing value is a flag. + assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || + (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && + Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == + MVT::Flag)) && "Lowering call/formal_arguments produced unexpected # results!"); // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to // remember that we legalized all of them, so it doesn't get relegalized. for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { + if (Tmp3.Val->getValueType(i) == MVT::Flag) + continue; Tmp1 = LegalizeOp(Tmp3.getValue(i)); if (Op.ResNo == i) Tmp2 = Tmp1; @@ -1472,6 +1480,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" " not tell us which reg is the stack pointer!"); SDOperand Chain = Tmp1.getOperand(0); + + // Chain the dynamic stack allocation so that it doesn't modify the stack + // pointer when other instructions are using the stack. + Chain = DAG.getCALLSEQ_START(Chain, + DAG.getConstant(0, TLI.getPointerTy())); + SDOperand Size = Tmp2.getOperand(1); SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); Chain = SP.getValue(1); @@ -1482,7 +1496,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { SP = DAG.getNode(ISD::AND, VT, SP, DAG.getConstant(-(uint64_t)Align, VT)); Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value - Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain + Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain + + Tmp2 = + DAG.getCALLSEQ_END(Chain, + DAG.getConstant(0, TLI.getPointerTy()), + DAG.getConstant(0, TLI.getPointerTy()), + SDOperand()); + Tmp1 = LegalizeOp(Tmp1); Tmp2 = LegalizeOp(Tmp2); break; diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index fd2550229e3..d1cd8c0c636 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -605,10 +605,10 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); - SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag }; - Chain = DAG.getNode(ISD::CALLSEQ_END, - DAG.getNodeValueTypes(MVT::Other, MVT::Flag), - ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3); + Chain = DAG.getCALLSEQ_END(Chain, + DAG.getConstant(NumBytes, MVT::i32), + DAG.getConstant(0, MVT::i32), + InFlag); if (RetVT != MVT::Other) InFlag = Chain.getValue(1); diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 8ff610eec55..ff82ec43445 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -17,7 +17,9 @@ // // Type profiles. -def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; +def SDT_ARMCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; +def SDT_ARMCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>, + SDTCisVT<1, i32> ]>; def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; @@ -45,10 +47,10 @@ def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; -def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, +def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq_start, [SDNPHasChain, SDNPOutFlag]>; -def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, - [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; +def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq_end, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; @@ -663,9 +665,9 @@ PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, let Defs = [SP], Uses = [SP] in { def ADJCALLSTACKUP : -PseudoInst<(outs), (ins i32imm:$amt, pred:$p), - "@ ADJCALLSTACKUP $amt", - [(ARMcallseq_end imm:$amt)]>; +PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), + "@ ADJCALLSTACKUP $amt1", + [(ARMcallseq_end imm:$amt1, imm:$amt2)]>; def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i32imm:$amt, pred:$p), diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index bc8161a1fed..7cfec81c868 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -162,9 +162,9 @@ def t_addrmode_sp : Operand, let Defs = [SP], Uses = [SP] in { def tADJCALLSTACKUP : -PseudoInst<(outs), (ins i32imm:$amt), - "@ tADJCALLSTACKUP $amt", - [(ARMcallseq_end imm:$amt)]>, Requires<[IsThumb]>; +PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), + "@ tADJCALLSTACKUP $amt1", + [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb]>; def tADJCALLSTACKDOWN : PseudoInst<(outs), (ins i32imm:$amt), diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 0d0f1d07ced..b4cd0c79dd2 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -769,10 +769,13 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, bool isThumb = AFI->isThumbFunction(); ARMCC::CondCodes Pred = isThumb ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue(); - unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg(); if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { + // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. + unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg(); emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII); } else { + // Note: PredReg is operand 3 for ADJCALLSTACKUP. + unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg(); assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII); } diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index a7626e61272..bfd65d746e2 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -374,8 +374,10 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size()); Chain = TheCall.getValue(RetTyVT != MVT::isVoid); - Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, - DAG.getConstant(NumBytes, getPointerTy())); + Chain = DAG.getCALLSEQ_END(Chain, + DAG.getConstant(NumBytes, getPointerTy()), + DAG.getConstant(0, getPointerTy()), + SDOperand()); SDOperand RetVal = TheCall; if (RetTyVT != ActualRetTyVT) { diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index f73875062ab..1ab6d4c6697 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -30,11 +30,14 @@ def retflag : SDNode<"AlphaISD::RET_FLAG", SDTRet, [SDNPHasChain, SDNPOptInFlag]>; // These are target-independent nodes, but have target-specific formats. -def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>; -def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeq, +def SDT_AlphaCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>; +def SDT_AlphaCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i64>, + SDTCisVT<1, i64> ]>; + +def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeq_start, [SDNPHasChain, SDNPOutFlag]>; -def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AlphaCallSeq, - [SDNPHasChain, SDNPOutFlag]>; +def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AlphaCallSeq_end, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; //******************** //Paterns for matching @@ -148,11 +151,14 @@ def IDEF_F64 : PseudoInstAlpha<(outs F8RC:$RA), (ins), ";#idef $RA", def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>; let isLoad = 1, hasCtrlDep = 1, Defs = [R30], Uses = [R30] in { -def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt), "; ADJUP $amt", +def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt), + "; ADJUP $amt", [(callseq_start imm:$amt)], s_pseudo>; -def ADJUSTSTACKDOWN : PseudoInstAlpha<(outs), (ins s64imm:$amt), "; ADJDOWN $amt", - [(callseq_end imm:$amt)], s_pseudo>; +def ADJUSTSTACKDOWN : PseudoInstAlpha<(outs), (ins s64imm:$amt1, s64imm:$amt2), + "; ADJDOWN $amt1", + [(callseq_end imm:$amt1, imm:$amt2)], s_pseudo>; } + def ALTENT : PseudoInstAlpha<(outs), (ins s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>; def PCLABEL : PseudoInstAlpha<(outs), (ins s64imm:$num), "PCMARKER_$num:\n",[], s_pseudo>; def MEMLABEL : PseudoInstAlpha<(outs), (ins s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m), diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 82cbd9c2118..92783de28be 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -535,9 +535,10 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, } } - Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, - DAG.getConstant(NumBytes, getPointerTy())); - + Chain = DAG.getCALLSEQ_END(Chain, + DAG.getConstant(NumBytes, getPointerTy()), + DAG.getConstant(0, getPointerTy()), + SDOperand()); return std::make_pair(RetVal, Chain); } diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index d12d30b43b2..d0a5ed750ff 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -399,12 +399,10 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) } // Create the CALLSEQ_END node. - NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); - Ops.clear(); - Ops.push_back(Chain); - Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); - Ops.push_back(InFlag); - Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); + Chain = DAG.getCALLSEQ_END(Chain, + DAG.getConstant(NumBytes, getPointerTy()), + DAG.getConstant(0, getPointerTy()), + InFlag); InFlag = Chain.getValue(1); // Handle result values, copying them out of physregs into vregs that we diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 3d7504b4add..1252912a1df 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -34,11 +34,14 @@ def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain, SDNPOptInFlag]>; // These are target-independent nodes, but have target-specific formats. -def SDT_MipsCallSeq : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; -def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq, - [SDNPHasChain, SDNPOutFlag]>; -def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq, +def SDT_MipsCallSeq_start : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; +def SDT_MipsCallSeq_end : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; + +def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq_start, [SDNPHasChain, SDNPOutFlag]>; +def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq_end, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; //===----------------------------------------------------------------------===// // Mips Instruction Predicate Definitions. @@ -348,9 +351,9 @@ let Defs = [SP], Uses = [SP] in { def ADJCALLSTACKDOWN : PseudoInstMips<(outs), (ins uimm16:$amt), "!ADJCALLSTACKDOWN $amt", [(callseq_start imm:$amt)]>; -def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt), - "!ADJCALLSTACKUP $amt", - [(callseq_end imm:$amt)]>; +def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt1, uimm16:$amt2), + "!ADJCALLSTACKUP $amt1", + [(callseq_end imm:$amt1, imm:$amt2)]>; } def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins), diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 9c2016ce79f..4d577adfc6e 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1816,6 +1816,13 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); + Chain = DAG.getCALLSEQ_END(Chain, + DAG.getConstant(NumBytes, PtrVT), + DAG.getConstant(0, PtrVT), + InFlag); + if (Op.Val->getValueType(0) != MVT::Other) + InFlag = Chain.getValue(1); + SDOperand ResultVals[3]; unsigned NumResults = 0; NodeTys.clear(); @@ -1878,8 +1885,6 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, break; } - Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, - DAG.getConstant(NumBytes, PtrVT)); NodeTys.push_back(MVT::Other); // If the function returns void, just return the chain. diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 77e00e57761..42d0f659ea8 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -23,8 +23,9 @@ def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> ]>; -def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; - +def SDT_PPCCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; +def SDT_PPCCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>, + SDTCisVT<1, i32> ]>; def SDT_PPCvperm : SDTypeProfile<1, 3, [ SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> ]>; @@ -90,10 +91,10 @@ def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>; // These are target-independent nodes, but have target-specific formats. -def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq, - [SDNPHasChain, SDNPOutFlag]>; -def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq, +def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq_start, [SDNPHasChain, SDNPOutFlag]>; +def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq_end, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall, @@ -318,9 +319,9 @@ let Defs = [R1], Uses = [R1] in { def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "${:comment} ADJCALLSTACKDOWN", [(callseq_start imm:$amt)]>; -def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt), +def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "${:comment} ADJCALLSTACKUP", - [(callseq_end imm:$amt)]>; + [(callseq_end imm:$amt1, imm:$amt2)]>; } def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 223f39807d7..f85c95b0725 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -675,9 +675,10 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, } } - Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, - DAG.getConstant(ArgsSize, getPointerTy())); - + Chain = DAG.getCALLSEQ_END(Chain, + DAG.getConstant(ArgsSize, getPointerTy()), + DAG.getConstant(0, getPointerTy()), + SDOperand()); return std::make_pair(RetVal, Chain); } diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index c41c191a5d8..101ca42c9ab 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -114,11 +114,14 @@ def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>; def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>; // These are target-independent nodes, but have target-specific formats. -def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; -def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq, - [SDNPHasChain, SDNPOutFlag]>; -def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq, +def SDT_SPCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; +def SDT_SPCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>, + SDTCisVT<1, i32> ]>; + +def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq_start, [SDNPHasChain, SDNPOutFlag]>; +def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq_end, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; def call : SDNode<"SPISD::CALL", SDT_SPCall, @@ -205,9 +208,9 @@ let Defs = [O6], Uses = [O6] in { def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), "!ADJCALLSTACKDOWN $amt", [(callseq_start imm:$amt)]>; -def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt), - "!ADJCALLSTACKUP $amt", - [(callseq_end imm:$amt)]>; +def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), + "!ADJCALLSTACKUP $amt1", + [(callseq_end imm:$amt1, imm:$amt2)]>; } def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins), "!IMPLICIT_DEF $dst", diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d51c1d97a3e..27decaab308 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1131,14 +1131,12 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, // This is common for Darwin/X86, Linux & Mingw32 targets. NumBytesForCalleeToPush = isSRet ? 4 : 0; } - - NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); - Ops.clear(); - Ops.push_back(Chain); - Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); - Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy())); - Ops.push_back(InFlag); - Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); + + Chain = DAG.getCALLSEQ_END(Chain, + DAG.getConstant(NumBytes, getPointerTy()), + DAG.getConstant(NumBytesForCalleeToPush, + getPointerTy()), + InFlag); InFlag = Chain.getValue(1); // Handle result values, copying them out of physregs into vregs that we diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 43ad9b04728..fb9fefa2f19 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -253,7 +253,8 @@ def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become sub / add // which can clobber EFLAGS. let Defs = [ESP, EFLAGS], Uses = [ESP] in { -def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt), "#ADJCALLSTACKDOWN", +def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt), + "#ADJCALLSTACKDOWN", [(X86callseq_start imm:$amt)]>; def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), "#ADJCALLSTACKUP", -- 2.34.1