From 0e910d2cb5feac287c2a3050c1945a3c4a3d2dd5 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Tue, 6 Aug 2013 17:03:03 +0000 Subject: [PATCH] Add PPC64 mulli pattern The PPC backend had been missing a pattern to generate mulli for 64-bit multiples. We had been generating it only for 32-bit multiplies. Unfortunately, generating li + mulld unnecessarily increases register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187807 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstr64Bit.td | 3 +++ test/CodeGen/PowerPC/mulli64.ll | 16 ++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 test/CodeGen/PowerPC/mulli64.ll diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index f04820ad523..f78bb3873ee 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -542,6 +542,9 @@ defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), "mulld", "$rT, $rA, $rB", IntMulHD, [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; +def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), + "mulli $rD, $rA, $imm", IntMulLI, + [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; } let neverHasSideEffects = 1 in { diff --git a/test/CodeGen/PowerPC/mulli64.ll b/test/CodeGen/PowerPC/mulli64.ll new file mode 100644 index 00000000000..21bc9cc3770 --- /dev/null +++ b/test/CodeGen/PowerPC/mulli64.ll @@ -0,0 +1,16 @@ +; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i64 @foo(i64 %a) #0 { +entry: + %mul = mul nsw i64 %a, 3 + ret i64 %mul +} + +; CHECK-LABEL: @foo +; CHECK: mulli 3, 3, 3 +; CHECK: blr + +attributes #0 = { nounwind readnone } + -- 2.34.1