From 0d8ba3303b40a150f70ff63f04f57160984492c1 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 18 Jun 2010 16:49:33 +0000 Subject: [PATCH] Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 does for {flags}. If we create virtual registers of the CCR class, RegAllocFast may try to spill them, and we can't do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 2 +- test/CodeGen/ARM/crash-O0.ll | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/ARM/crash-O0.ll diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 2d963fa9703..5ec995f771c 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -4945,7 +4945,7 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, } } if (StringRef("{cc}").equals_lower(Constraint)) - return std::make_pair(0U, ARM::CCRRegisterClass); + return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } diff --git a/test/CodeGen/ARM/crash-O0.ll b/test/CodeGen/ARM/crash-O0.ll new file mode 100644 index 00000000000..4f0f39fe38a --- /dev/null +++ b/test/CodeGen/ARM/crash-O0.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv6-apple-darwin10" + +%struct0 = type { i32, i32 } + +; This function would crash RegAllocFast because it tried to spill %CPSR. +define arm_apcscc void @clobber_cc() nounwind noinline ssp { +entry: + %asmtmp = call %struct0 asm sideeffect "...", "=&r,=&r,r,Ir,r,~{cc},~{memory}"(i32* undef, i32 undef, i32 1) nounwind ; <%0> [#uses=0] + unreachable +} -- 2.34.1