From 0abc41459444a0a84eaa4739c05874bf9e115592 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 25 Jan 2016 15:33:43 +0800 Subject: [PATCH] UPSTREAM: arm64: dts: rockchip: add rk3368 tuning clk for emmc and sdmmc Add tuning clk for emmc and sdmmc, otherwise I get the following failure while enabling mmc-hs200-1_8v. dwmmc_rockchip ff0f0000.dwmmc: Tuning clock (sample_clk) not defined. mmc0: tuning execution failed mmc0: error -5 whilst initialising MMC card With it dwmmc_rockchip ff0f0000.dwmmc: Successfully tuned phase to 170 mmc0: new HS200 MMC card at address 0001 mmcblk0: mmc0:0001 M8G1GC 7.28 GiB Change-Id: I14534f43249edecbb8239f4a86c808ebb7f0a959 Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner (cherry picked from commit 90191625ec0d075ac0748181ae1b947b0b30297e) --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 5c0953798535..5bced1c3bbeb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -335,8 +335,9 @@ compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>; clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; status = "disabled"; @@ -358,8 +359,9 @@ compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0f0000 0x0 0x4000>; clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; - clock-names = "biu", "ciu"; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; status = "disabled"; -- 2.34.1