From 085e440316bafa1766543aa4dff2a6972c5709d4 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Wed, 5 Aug 2015 15:18:58 +0000 Subject: [PATCH] [AArch64] Register (existing) AArch64AdvSIMDScalar pass with LLVM pass manager. Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass. IIRC, this pass is off by default, but it's still helpful when debugging. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244056 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp b/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp index 18d21fd3861..563ebda66da 100644 --- a/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp +++ b/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp @@ -61,6 +61,12 @@ STATISTIC(NumScalarInsnsUsed, "Number of scalar instructions used"); STATISTIC(NumCopiesDeleted, "Number of cross-class copies deleted"); STATISTIC(NumCopiesInserted, "Number of cross-class copies inserted"); +namespace llvm { +void initializeAArch64AdvSIMDScalarPass(PassRegistry &); +} + +#define AARCH64_ADVSIMD_NAME "AdvSIMD Scalar Operation Optimization" + namespace { class AArch64AdvSIMDScalar : public MachineFunctionPass { MachineRegisterInfo *MRI; @@ -82,12 +88,14 @@ private: public: static char ID; // Pass identification, replacement for typeid. - explicit AArch64AdvSIMDScalar() : MachineFunctionPass(ID) {} + explicit AArch64AdvSIMDScalar() : MachineFunctionPass(ID) { + initializeAArch64AdvSIMDScalarPass(*PassRegistry::getPassRegistry()); + } bool runOnMachineFunction(MachineFunction &F) override; const char *getPassName() const override { - return "AdvSIMD Scalar Operation Optimization"; + return AARCH64_ADVSIMD_NAME; } void getAnalysisUsage(AnalysisUsage &AU) const override { @@ -98,6 +106,9 @@ public: char AArch64AdvSIMDScalar::ID = 0; } // end anonymous namespace +INITIALIZE_PASS(AArch64AdvSIMDScalar, "aarch64-simd-scalar", + AARCH64_ADVSIMD_NAME, false, false) + static bool isGPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI) { if (SubReg) -- 2.34.1