From 0719499a77b9818cf9c0cc7a779c7b58bcaf7f37 Mon Sep 17 00:00:00 2001 From: wdc Date: Thu, 3 Jul 2014 17:49:06 +0800 Subject: [PATCH] 3036: add cru,grf,iomap --- arch/arm/mach-rockchip/rk3036.c | 82 ++++++++++++++++++++++++++----- include/linux/rockchip/cru.h | 24 ++++++++++ include/linux/rockchip/grf.h | 85 +++++++++++++++++++++++++++++++++ include/linux/rockchip/iomap.h | 4 +- 4 files changed, 182 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3036.c b/arch/arm/mach-rockchip/rk3036.c index fc8b01faccaa..f0515512eaeb 100644 --- a/arch/arm/mach-rockchip/rk3036.c +++ b/arch/arm/mach-rockchip/rk3036.c @@ -48,24 +48,55 @@ .type = MT_DEVICE, \ } - +#define RK3036_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K) #define RK3036_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0) -static const char * const rk3036_dt_compat[] __initconst = { - "rockchip,rk3036", - NULL, -}; static struct map_desc rk3036_io_desc[] __initdata = { RK3036_DEVICE(TIMER), + RK3036_DEVICE(CRU), + RK3036_DEVICE(GRF), + RK3036_DEVICE(ROM), + RK3036_DEVICE(EFUSE), + RK_DEVICE(RK_DDR_VIRT, RK3036_DDR_PCTL_PHYS, RK3036_DDR_PCTL_SIZE), + RK_DEVICE(RK_DDR_VIRT + RK3036_DDR_PCTL_SIZE, RK3036_DDR_PHY_PHYS, RK3036_DDR_PHY_SIZE), + RK_DEVICE(RK_GPIO_VIRT(0), RK3036_GPIO0_PHYS, RK3036_GPIO_SIZE), + RK_DEVICE(RK_GPIO_VIRT(1), RK3036_GPIO1_PHYS, RK3036_GPIO_SIZE), + RK_DEVICE(RK_GPIO_VIRT(2), RK3036_GPIO2_PHYS, RK3036_GPIO_SIZE), + RK_DEVICE(RK_DEBUG_UART_VIRT, RK3036_UART2_PHYS, RK3036_UART_SIZE), + RK_DEVICE(RK_GIC_VIRT, RK3036_GIC_DIST_PHYS, RK3036_GIC_DIST_SIZE), + RK_DEVICE(RK_GIC_VIRT + RK3036_GIC_DIST_SIZE,RK3036_GIC_CPU_PHYS, RK3036_GIC_CPU_SIZE), + RK_DEVICE(RK_BOOTRAM_VIRT, RK3036_IMEM_PHYS, RK3036_IMEM_SIZE), + RK_DEVICE(RK3036_IMEM_VIRT, RK3036_IMEM_PHYS, SZ_4K), + RK_DEVICE(RK_TIMER_VIRT, RK3036_TIMER_PHYS, RK3036_TIMER_SIZE), }; +static void __init rk3036_boot_mode_init(void) +{ + u32 flag = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG0); + u32 mode = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG1); + u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3036_CRU_RST_ST); + + if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER)) + mode = BOOT_MODE_RECOVERY; + if (rst_st & ((1 << 2) | (1 << 3))) + mode = BOOT_MODE_WATCHDOG; + rockchip_boot_mode_init(flag, mode); +} + +static void usb_uart_init(void) +{ + return; +} + static void __init rk3036_dt_map_io(void) { rockchip_soc_id = ROCKCHIP_SOC_RK3036; iotable_init(rk3036_io_desc, ARRAY_SIZE(rk3036_io_desc)); - debug_ll_io_init(); + debug_ll_io_init(); + usb_uart_init(); + /* enable timer5 for core */ writel_relaxed(0, RK3036_TIMER5_VIRT + 0x10); dsb(); @@ -74,6 +105,8 @@ static void __init rk3036_dt_map_io(void) dsb(); writel_relaxed(1, RK3036_TIMER5_VIRT + 0x10); dsb(); + + rk3036_boot_mode_init(); } static int rk3036_sys_set_power_domain(enum pmu_power_domain pd, bool on) @@ -83,7 +116,7 @@ static int rk3036_sys_set_power_domain(enum pmu_power_domain pd, bool on) static bool rk3036_pmu_power_domain_is_on(enum pmu_power_domain pd) { - return 0; + return 1; } static int rk3036_pmu_set_idle_request(enum pmu_idle_req req, bool idle) @@ -93,24 +126,48 @@ static int rk3036_pmu_set_idle_request(enum pmu_idle_req req, bool idle) static void __init rk3036_dt_init_timer(void) { - rockchip_pmu_ops.set_power_domain = rk3036_sys_set_power_domain; - rockchip_pmu_ops.power_domain_is_on = rk3036_pmu_power_domain_is_on; - rockchip_pmu_ops.set_idle_request = rk3036_pmu_set_idle_request; + rockchip_pmu_ops.set_power_domain = rk3036_sys_set_power_domain; + rockchip_pmu_ops.power_domain_is_on = rk3036_pmu_power_domain_is_on; + rockchip_pmu_ops.set_idle_request = rk3036_pmu_set_idle_request; + of_clk_init(NULL); clocksource_of_init(); } -static void __init rk3036_reserve(void) +static void __init rk3036_init_late(void) { + return; } -static void __init rk3036_init_late(void) +static void __init rk3036_reserve(void) { + /* reserve memory for ION */ + //rockchip_ion_reserve(); + + return; } static void rk3036_restart(char mode, const char *cmd) { + u32 boot_flag, boot_mode; + + rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode); + + writel_relaxed(boot_flag, RK_GRF_VIRT + RK3036_GRF_OS_REG0); // for loader + writel_relaxed(boot_mode, RK_GRF_VIRT + RK3036_GRF_OS_REG1); // for linux + dsb(); + + /* pll enter slow mode */ + //writel_relaxed(0xf3030000, RK_CRU_VIRT + RK3288_CRU_MODE_CON); + //dsb(); + //writel_relaxed(0xeca8, RK_CRU_VIRT + RK3288_CRU_GLB_SRST_SND_VALUE); + //dsb(); } +static const char * const rk3036_dt_compat[] __initconst = { + "rockchip,rk3036", + NULL, +}; + DT_MACHINE_START(RK3036_DT, "Rockchip RK3036") .dt_compat = rk3036_dt_compat, .smp = smp_ops(rockchip_smp_ops), @@ -118,5 +175,6 @@ DT_MACHINE_START(RK3036_DT, "Rockchip RK3036") .map_io = rk3036_dt_map_io, .init_time = rk3036_dt_init_timer, .init_late = rk3036_init_late, + .reserve = rk3036_reserve, .restart = rk3036_restart, MACHINE_END diff --git a/include/linux/rockchip/cru.h b/include/linux/rockchip/cru.h index e5d355b7e06c..74d03bb36dcb 100755 --- a/include/linux/rockchip/cru.h +++ b/include/linux/rockchip/cru.h @@ -322,6 +322,7 @@ enum rk3288_cru_soft_reset { RK3288_SOFT_RST_TSP_27M, }; + static inline void rk3288_cru_set_soft_reset(enum rk3288_cru_soft_reset idx, bool on) { void __iomem *reg = RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(idx >> 4); @@ -330,4 +331,27 @@ static inline void rk3288_cru_set_soft_reset(enum rk3288_cru_soft_reset idx, boo dsb(); } +#define RK3036_CRU_GLB_SRST_FST_VALUE 0x00100 +#define RK3036_CRU_GLB_SRST_SND_VALUE 0x00104 +#define RK3036_CRU_SOFTRST0_CON 0x00110 +#define RK3036_CRU_SOFTRST1_CON 0x00114 +#define RK3036_CRU_SOFTRST2_CON 0x00118 +#define RK3036_CRU_SOFTRST3_CON 0x0011c +#define RK3036_CRU_SOFTRST4_CON 0x00120 +#define RK3036_CRU_SOFTRST5_CON 0x00124 +#define RK3036_CRU_SOFTRST6_CON 0x00128 +#define RK3036_CRU_SOFTRST7_CON 0x0012c +#define RK3036_CRU_SOFTRST8_CON 0x00130 +#define RK3036_CRU_MISC_CON 0x00134 +#define RK3036_CRU_GLB_CNT_TH 0x00140 +#define RK3036_CRU_SDMMC_CON0 0x00144 +#define RK3036_CRU_SDMMC_CON1 0x00148 +#define RK3036_CRU_SDIO_CON0 0x0014c +#define RK3036_CRU_SDIO_CON1 0x00150 +#define RK3036_CRU_EMMC_CON0 0x00154 +#define RK3036_CRU_EMMC_CON1 0x00158 +#define RK3036_CRU_RST_ST 0x00160 +#define RK3036_CRU_PLL_MASK_CON 0x001f0 + + #endif diff --git a/include/linux/rockchip/grf.h b/include/linux/rockchip/grf.h index 681919768552..bfa788cd4e1e 100755 --- a/include/linux/rockchip/grf.h +++ b/include/linux/rockchip/grf.h @@ -339,4 +339,89 @@ #define RK3288_SGRF_FAST_BOOT_ADDR 0x0120 + +#define RK3036_GRF_GPIO0A_IOMUX 0x000a8 +#define RK3036_GRF_GPIO0B_IOMUX 0x000ac +#define RK3036_GRF_GPIO0C_IOMUX 0x000b0 +#define RK3036_GRF_GPIO0D_IOMUX 0x000b4 +#define RK3036_GRF_GPIO1A_IOMUX 0x000b8 +#define RK3036_GRF_GPIO1B_IOMUX 0x000bc +#define RK3036_GRF_GPIO1C_IOMUX 0x000c0 +#define RK3036_GRF_GPIO1D_IOMUX 0x000c4 +#define RK3036_GRF_GPIO2A_IOMUX 0x000c8 +#define RK3036_GRF_GPIO2B_IOMUX 0x000cc +#define RK3036_GRF_GPIO2C_IOMUX 0x000d0 +#define RK3036_GRF_GPIO2D_IOMUX 0x000d4 +#define RK3036_GRF_GPIO_DS 0x00100 +#define RK3036_GRF_GPIO0L_PULL 0x00118 +#define RK3036_GRF_GPIO0H_PULL 0x0011c +#define RK3036_GRF_GPIO1L_PULL 0x00120 +#define RK3036_GRF_GPIO1H_PULL 0x00124 + +#define RK3036_GRF_GPIO2L_PULL 0x00128 +#define RK3036_GRF_GPIO2H_PULL 0x0012c +#define RK3036_GRF_SOC_CON0 0x00140 +#define RK3036_GRF_SOC_CON1 0x00144 +#define RK3036_GRF_SOC_CON2 0x00148 +#define RK3036_GRF_SOC_STATUS0 0x0014c +#define RK3036_GRF_SOC_CON3 0x00154 +#define RK3036_GRF_DMAC_CON0 0x0015c +#define RK3036_GRF_DMAC_CON1 0x00160 +#define RK3036_GRF_DMAC_CON2 0x00164 +#define RK3036_GRF_UOC0_CON5 0x0017c +#define RK3036_GRF_UOC1_CON4 0x00190 +#define RK3036_GRF_UOC1_CON5 0x00194 +#define RK3036_GRF_DDRC_STAT 0x0019c +#define RK3036_GRF_UOC_CON6 0x001a0 +#define RK3036_GRF_SOC_STATUS1 0x001a4 +#define RK3036_GRF_CPU_CON0 0x001a8 +#define RK3036_GRF_CPU_CON1 0x001ac +#define RK3036_GRF_CPU_CON2 0x001b0 +#define RK3036_GRF_CPU_CON3 0x001b4 +#define RK3036_GRF_CPU_STATUS0 0x001c0 +#define RK3036_GRF_CPU_STATUS1 0x001c4 +#define RK3036_GRF_OS_REG0 0x001c8 +#define RK3036_GRF_OS_REG1 0x001cc +#define RK3036_GRF_OS_REG2 0x001d0 +#define RK3036_GRF_OS_REG3 0x001d4 +#define RK3036_GRF_OS_REG4 0x001d8 +#define RK3036_GRF_OS_REG5 0x001dc +#define RK3036_GRF_OS_REG6 0x001e0 +#define RK3036_GRF_OS_REG7 0x001e4 +#define RK3036_GRF_DLL_CON0 0x00200 +#define RK3036_GRF_DLL_CON1 0x00204 +#define RK3036_GRF_DLL_CON2 0x00208 +#define RK3036_GRF_DLL_CON3 0x0020c +#define RK3036_GRF_DLL_STATUS0 0x00210 +#define RK3036_GRF_DLL_STATUS1 0x00214 + +#define RK3036_GRF_DLL_STATUS2 0x00218 +#define RK3036_GRF_DLL_STATUS3 0x0021c +#define RK3036_GRF_DFI_WRNUM 0x00220 +#define RK3036_GRF_DFI_RDNUM 0x00224 +#define RK3036_GRF_DFI_ACTNUM 0x00228 +#define RK3036_GRF_DFI_TIMERVAL 0x0022c +#define RK3036_GRF_NIF_FIFO0 0x00230 +#define RK3036_GRF_NIF_FIFO1 0x00234 +#define RK3036_GRF_NIF_FIFO2 0x00238 +#define RK3036_GRF_NIF_FIFO3 0x0023c +#define RK3036_GRF_USBPHY0_CON0 0x00280 +#define RK3036_GRF_USBPHY0_CON1 0x00284 +#define RK3036_GRF_USBPHY0_CON2 0x00288 +#define RK3036_GRF_USBPHY0_CON3 0x0028c +#define RK3036_GRF_USBPHY0_CON4 0x00290 +#define RK3036_GRF_USBPHY0_CON5 0x00294 +#define RK3036_GRF_USBPHY0_CON6 0x00298 +#define RK3036_GRF_USBPHY0_CON7 0x0029c +#define RK3036_GRF_USBPHY1_CON0 0x002a0 +#define RK3036_GRF_USBPHY1_CON1 0x002a4 +#define RK3036_GRF_USBPHY1_CON2 0x002a8 +#define RK3036_GRF_USBPHY1_CON3 0x002ac +#define RK3036_GRF_USBPHY1_CON4 0x002b0 +#define RK3036_GRF_USBPHY1_CON5 0x002b4 +#define RK3036_GRF_USBPHY1_CON6 0x002b8 + +#define RK3036_GRF_USBPHY1_CON7 0x002bc +#define RK3036_GRF_CHIP_TAG 0x00300 +#define RK3036_GRF_SDMMC_DET_CNT 0x00304 #endif diff --git a/include/linux/rockchip/iomap.h b/include/linux/rockchip/iomap.h index d6c9047edc3a..ac555eef33bd 100755 --- a/include/linux/rockchip/iomap.h +++ b/include/linux/rockchip/iomap.h @@ -116,7 +116,7 @@ #define RK3036_IMEM_PHYS 0x10080000 #define RK3036_IMEM_SIZE SZ_8K #define RK3036_ROM_PHYS 0x10100000 -#define RK3036_ROM_SIZe SZ_16K +#define RK3036_ROM_SIZE SZ_16K #define RK3036_CPU_AXI_BUS_PHYS 0x10128000 #define RK3036_CPU_AXI_BUS_SIZE SZ_32K #define RK3036_GIC_DIST_PHYS 0x10139000 @@ -127,6 +127,8 @@ #define RK3036_CRU_SIZE SZ_4K #define RK3036_DDR_PCTL_PHYS 0x20040000 #define RK3036_DDR_PCTL_SIZE SZ_4K +#define RK3036_GRF_PHYS 0x20080000 +#define RK3036_GRF_SIZE SZ_4K #define RK3036_DDR_PHY_PHYS 0x200a0000 #define RK3036_DDR_PHY_SIZE SZ_4K #define RK3036_TIMER_PHYS 0x20044000 -- 2.34.1