From 02c602b333ed2a1a13a17981f3c3f2f5463d5e5c Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Wed, 16 May 2007 21:53:07 +0000
Subject: [PATCH] PredicateInstruction returns true if the operation was
 successful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/Target/TargetInstrInfo.h |  4 ++--
 lib/Target/ARM/ARMInstrInfo.cpp       | 10 +++++---
 lib/Target/ARM/ARMInstrInfo.h         |  2 +-
 lib/Target/TargetInstrInfo.cpp        | 33 +++++++++++++++------------
 4 files changed, 29 insertions(+), 20 deletions(-)

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 7c2cfac8359..00a05569b95 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -390,8 +390,8 @@ public:
   }
 
   /// PredicateInstruction - Convert the instruction into a predicated
-  /// instruction.
-  virtual void PredicateInstruction(MachineInstr *MI,
+  /// instruction. It returns true if the operation was successful.
+  virtual bool PredicateInstruction(MachineInstr *MI,
                                     std::vector<MachineOperand> &Cond) const;
 
   /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index b631124b6eb..891ae558f3d 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -423,17 +423,21 @@ ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
   return false;
 }
 
-void ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
+bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
                                       std::vector<MachineOperand> &Cond) const {
   unsigned Opc = MI->getOpcode();
   if (Opc == ARM::B || Opc == ARM::tB) {
     MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
     MI->addImmOperand(Cond[0].getImmedValue());
-    return;
+    return true;
   }
 
   MachineOperand *PMO = MI->findFirstPredOperand();
-  PMO->setImm(Cond[0].getImmedValue());
+  if (PMO) {
+    PMO->setImm(Cond[0].getImmedValue());
+    return true;
+  }
+  return false;
 }
 
 
diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h
index cb0b812e161..33645b2d334 100644
--- a/lib/Target/ARM/ARMInstrInfo.h
+++ b/lib/Target/ARM/ARMInstrInfo.h
@@ -104,7 +104,7 @@ public:
   virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
 
   // Predication support.
-  virtual void PredicateInstruction(MachineInstr *MI,
+  virtual bool PredicateInstruction(MachineInstr *MI,
                                     std::vector<MachineOperand> &Cond) const;
 };
 
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index fe5ee1d25e0..d1413510fff 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -60,22 +60,27 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
   return MI;
 }
 
-void TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
+bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
                                       std::vector<MachineOperand> &Cond) const {
+  bool MadeChange = false;
   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
-  assert((TID->Flags & M_PREDICABLE) &&
-         "Predicating an unpredicable instruction!");
-
-  for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
-    if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
-      MachineOperand &MO = MI->getOperand(i);
-      if (MO.isReg())
-        MO.setReg(Cond[j].getReg());
-      else if (MO.isImm())
-        MO.setImm(Cond[j].getImmedValue());
-      else if (MO.isMBB())
-        MO.setMachineBasicBlock(Cond[j].getMachineBasicBlock());
-      ++j;
+  if (TID->Flags & M_PREDICABLE) {
+    for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
+      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+        MachineOperand &MO = MI->getOperand(i);
+        if (MO.isReg()) {
+          MO.setReg(Cond[j].getReg());
+          MadeChange = true;
+        } else if (MO.isImm()) {
+          MO.setImm(Cond[j].getImmedValue());
+          MadeChange = true;
+        } else if (MO.isMBB()) {
+          MO.setMachineBasicBlock(Cond[j].getMachineBasicBlock());
+          MadeChange = true;
+        }
+        ++j;
+      }
     }
   }
+  return MadeChange;
 }
-- 
2.34.1