From 01595c52b32b8e40b87dd9d36753f8e972ab6f74 Mon Sep 17 00:00:00 2001
From: Nate Begeman <natebegeman@mac.com>
Date: Sat, 26 Nov 2005 22:39:34 +0000
Subject: [PATCH] Small tweaks noticed while on the plane.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24492 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCInstrFormats.td | 6 ++++++
 lib/Target/PowerPC/PPCInstrInfo.td    | 7 +++----
 lib/Target/PowerPC/PPCRegisterInfo.td | 2 +-
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 8f93ac9fd3f..cba2aabe780 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -556,6 +556,8 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr,
   bits<5> VA;
   bits<5> VB;
   bits<5> VC;
+
+  let Pattern = pattern;
   
   let Inst{6-10}  = VD;
   let Inst{11-15} = VA;
@@ -572,6 +574,8 @@ class VXForm_1<bits<11> xo, dag OL, string asmstr,
   bits<5> VA;
   bits<5> VB;
   
+  let Pattern = pattern;
+  
   let Inst{6-10}  = VD;
   let Inst{11-15} = VA;
   let Inst{16-20} = VB;
@@ -586,6 +590,8 @@ class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr,
   bits<5> VA;
   bits<5> VB;
   
+  let Pattern = pattern;
+  
   let Inst{6-10}  = VD;
   let Inst{11-15} = VA;
   let Inst{16-20} = VB;
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index af6fb0d2853..c755a98e744 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -464,9 +464,9 @@ def EXTSB  : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
 def EXTSH  : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
                       "extsh $rA, $rS", IntGeneral,
                       [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
-def EXTSW  : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
-                      "extsw $rA, $rS", IntRotateD,
-                      []>, isPPC64;
+def EXTSW  : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
+                      "extsw $rA, $rS", IntGeneral,
+                      [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
 def CMP    : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
                       "cmp $crD, $long, $rA, $rB", IntCompare>;
 def CMPL   : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
@@ -794,7 +794,6 @@ def VXOR   : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vxor $vD, $vA, $vB", VecGeneral,
                       []>;
 
-
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Patterns
 //
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index c3fa558cc8c..abb021549b2 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -101,7 +101,7 @@ def F26 : FPR<26, "f26">;  def F27 : FPR<27, "f27">;
 def F28 : FPR<28, "f28">;  def F29 : FPR<29, "f29">;
 def F30 : FPR<30, "f30">;  def F31 : FPR<31, "f31">;
 
-// Floating-point registers
+// Vector registers
 def V0  : VR< 0,  "v0">;  def V1  : VR< 1,  "v1">;
 def V2  : VR< 2,  "v2">;  def V3  : VR< 3,  "v3">;
 def V4  : VR< 4,  "v4">;  def V5  : VR< 5,  "v5">;
-- 
2.34.1