From 5ea64fd9eb0027ad20a66ea29211eef79d8842a0 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 17 Aug 2006 22:00:08 +0000 Subject: [PATCH] Constify some methods. Patch provided by Anton Vayvod, thanks! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineFunction.h | 5 +++++ include/llvm/Target/MRegisterInfo.h | 4 ++-- lib/Target/ARM/ARMRegisterInfo.td | 4 ++-- lib/Target/Alpha/AlphaRegisterInfo.cpp | 2 +- lib/Target/Alpha/AlphaRegisterInfo.td | 12 ++++++------ lib/Target/IA64/IA64RegisterInfo.cpp | 2 +- lib/Target/IA64/IA64RegisterInfo.td | 16 ++++++++-------- lib/Target/PowerPC/PPCRegisterInfo.td | 16 ++++++++-------- lib/Target/Sparc/SparcRegisterInfo.td | 4 ++-- lib/Target/X86/X86RegisterInfo.cpp | 2 +- lib/Target/X86/X86RegisterInfo.td | 12 ++++++------ 11 files changed, 42 insertions(+), 37 deletions(-) diff --git a/include/llvm/CodeGen/MachineFunction.h b/include/llvm/CodeGen/MachineFunction.h index 0f511e3d917..340e2f936b4 100644 --- a/include/llvm/CodeGen/MachineFunction.h +++ b/include/llvm/CodeGen/MachineFunction.h @@ -165,6 +165,11 @@ public: return static_cast(MFInfo); } + template + const Ty *getInfo() const { + return const_cast(this)->getInfo(); + } + /// setUsedPhysRegs - The register allocator should call this to initialized /// the UsedPhysRegs set. This should be passed a new[]'d array with entries /// for all of the physical registers that the target supports. Each array diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index 151274c8e4e..707061f853a 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -170,10 +170,10 @@ public: /// /// By default, these methods return all registers in the class. /// - virtual iterator allocation_order_begin(MachineFunction &MF) const { + virtual iterator allocation_order_begin(const MachineFunction &MF) const { return begin(); } - virtual iterator allocation_order_end(MachineFunction &MF) const { + virtual iterator allocation_order_end(const MachineFunction &MF) const { return end(); } diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 5d61cc432fc..89a84f59274 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -45,11 +45,11 @@ def IntRegs : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15]> { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ IntRegsClass::iterator - IntRegsClass::allocation_order_end(MachineFunction &MF) const { + IntRegsClass::allocation_order_end(const MachineFunction &MF) const { // r15 == Program Counter // r14 == Link Register // r13 == Stack Pointer diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 9ea4b70893e..772840a3eb6 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -180,7 +180,7 @@ AlphaRegisterInfo::getCalleeSaveRegClasses() const { // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. // -static bool hasFP(MachineFunction &MF) { +static bool hasFP(const MachineFunction &MF) { MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->hasVarSizedObjects(); } diff --git a/lib/Target/Alpha/AlphaRegisterInfo.td b/lib/Target/Alpha/AlphaRegisterInfo.td index f6cea9ee4b8..9855ce27ca7 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.td +++ b/lib/Target/Alpha/AlphaRegisterInfo.td @@ -124,11 +124,11 @@ def GPRC : RegisterClass<"Alpha", [i64], 64, R15, R30, R31 ]> //zero { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ GPRCClass::iterator - GPRCClass::allocation_order_end(MachineFunction &MF) const { + GPRCClass::allocation_order_end(const MachineFunction &MF) const { return end()-3; } }]; @@ -142,11 +142,11 @@ def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1, F31 ]> //zero { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ F4RCClass::iterator - F4RCClass::allocation_order_end(MachineFunction &MF) const { + F4RCClass::allocation_order_end(const MachineFunction &MF) const { return end()-1; } }]; @@ -160,11 +160,11 @@ def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1, F31 ]> //zero { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ F8RCClass::iterator - F8RCClass::allocation_order_end(MachineFunction &MF) const { + F8RCClass::allocation_order_end(const MachineFunction &MF) const { return end()-1; } }]; diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index 578c0d101ee..7fcd502de9b 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -113,7 +113,7 @@ IA64RegisterInfo::getCalleeSaveRegClasses() const { // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. // -static bool hasFP(MachineFunction &MF) { +static bool hasFP(const MachineFunction &MF) { return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); } diff --git a/lib/Target/IA64/IA64RegisterInfo.td b/lib/Target/IA64/IA64RegisterInfo.td index bb71ec6b3f5..087c18f6480 100644 --- a/lib/Target/IA64/IA64RegisterInfo.td +++ b/lib/Target/IA64/IA64RegisterInfo.td @@ -422,18 +422,18 @@ def GR : RegisterClass<"IA64", [i64], 64, r0, r1, r2, r5, r12, r13, r22, rp]> // the last 16 are special (look down) { let MethodProtos = [{ - iterator allocation_order_begin(MachineFunction &MF) const; - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_begin(const MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ GRClass::iterator - GRClass::allocation_order_begin(MachineFunction &MF) const { + GRClass::allocation_order_begin(const MachineFunction &MF) const { // hide the 8 out? registers appropriately: return begin()+(8-(MF.getInfo()->outRegsUsed)); } GRClass::iterator - GRClass::allocation_order_end(MachineFunction &MF) const { + GRClass::allocation_order_end(const MachineFunction &MF) const { int numReservedRegs=8; // the 8 special registers r0,r1,r2,r5,r12,r13 etc // we also can't allocate registers for use as locals if they're @@ -472,17 +472,17 @@ def FP : RegisterClass<"IA64", [f64], 64, let Alignment=128; let MethodProtos = [{ - iterator allocation_order_begin(MachineFunction &MF) const; - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_begin(const MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ FPClass::iterator - FPClass::allocation_order_begin(MachineFunction &MF) const { + FPClass::allocation_order_begin(const MachineFunction &MF) const { return begin(); // we don't hide any FP regs from the start } FPClass::iterator - FPClass::allocation_order_end(MachineFunction &MF) const { + FPClass::allocation_order_end(const MachineFunction &MF) const { return end()-2; // we hide regs F0, F1 from the end } }]; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 5c6ac247c9e..07b022b2e75 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -209,16 +209,16 @@ def GPRC : RegisterClass<"PPC", [i32], 32, R16, R15, R14, R13, R31, R0, R1, LR]> { let MethodProtos = [{ - iterator allocation_order_begin(MachineFunction &MF) const; - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_begin(const MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ GPRCClass::iterator - GPRCClass::allocation_order_begin(MachineFunction &MF) const { + GPRCClass::allocation_order_begin(const MachineFunction &MF) const { return begin(); } GPRCClass::iterator - GPRCClass::allocation_order_end(MachineFunction &MF) const { + GPRCClass::allocation_order_end(const MachineFunction &MF) const { if (hasFP(MF)) return end()-4; // don't allocate R31, R0, R1, LR else @@ -232,16 +232,16 @@ def G8RC : RegisterClass<"PPC", [i64], 64, X16, X15, X14, X13, X31, X0, X1]> { let MethodProtos = [{ - iterator allocation_order_begin(MachineFunction &MF) const; - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_begin(const MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ G8RCClass::iterator - G8RCClass::allocation_order_begin(MachineFunction &MF) const { + G8RCClass::allocation_order_begin(const MachineFunction &MF) const { return begin(); } G8RCClass::iterator - G8RCClass::allocation_order_end(MachineFunction &MF) const { + G8RCClass::allocation_order_end(const MachineFunction &MF) const { if (hasFP(MF)) return end()-3; else diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index b9bf1bd75bd..11251e92581 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -138,11 +138,11 @@ def IntRegs : RegisterClass<"SP", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7, G5, G6, G7 // reserved for kernel ]> { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ IntRegsClass::iterator - IntRegsClass::allocation_order_end(MachineFunction &MF) const { + IntRegsClass::allocation_order_end(const MachineFunction &MF) const { // FIXME: These special regs should be taken out of the regclass! return end()-10 // Don't allocate special registers -1; // FIXME: G1 reserved for large imm generation by frame code. diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 760d3ff2188..90ca91d12a5 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -737,7 +737,7 @@ X86RegisterInfo::getCalleeSaveRegClasses() const { // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. // -static bool hasFP(MachineFunction &MF) { +static bool hasFP(const MachineFunction &MF) { return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects() || MF.getInfo()->getForceFramePointer()); diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 687268f9420..7a713c3110e 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -107,11 +107,11 @@ def GR8 : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH, BL, BH]>; def GR16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ GR16Class::iterator - GR16Class::allocation_order_end(MachineFunction &MF) const { + GR16Class::allocation_order_end(const MachineFunction &MF) const { if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? return end()-2; // If so, don't allocate SP or BP else @@ -123,11 +123,11 @@ def GR16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> { def GR32 : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ GR32Class::iterator - GR32Class::allocation_order_end(MachineFunction &MF) const { + GR32Class::allocation_order_end(const MachineFunction &MF) const { if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? return end()-2; // If so, don't allocate ESP or EBP else @@ -160,11 +160,11 @@ def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; def RST : RegisterClass<"X86", [f64], 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> { let MethodProtos = [{ - iterator allocation_order_end(MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ RSTClass::iterator - RSTClass::allocation_order_end(MachineFunction &MF) const { + RSTClass::allocation_order_end(const MachineFunction &MF) const { return begin(); } }]; -- 2.34.1