Chandler Carruth [Sat, 11 Jul 2015 04:39:00 +0000 (04:39 +0000)]
[PM/AA] Completely remove the AliasAnalysis::copyValue interface.
No in-tree alias analysis used this facility, and it was not called in
any particularly rigorous way, so it seems unlikely to be correct.
Note that one of the only stateful AA implementations in-tree,
GlobalsModRef is completely broken currently (and any AA passes like it
are equally broken) because Module AA passes are not effectively
invalidated when a function pass that fails to update the AA stack runs.
Ultimately, it doesn't seem like we know how we want to build stateful
AA, and until then trying to support and maintain correctness for an
untested API is essentially impossible. To that end, I'm planning to rip
out all of the update API. It can return if and when we need it and know
how to build it on top of the new pass manager and as part of *tested*
stateful AA implementations in the tree.
Differential Revision: http://reviews.llvm.org/D10889
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241975
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Lang Hames [Sat, 11 Jul 2015 02:07:28 +0000 (02:07 +0000)]
[ExecutionEngine] Add a static cast to the unittest for r241962 to suppress a
warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241974
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Lang Hames [Sat, 11 Jul 2015 01:59:04 +0000 (01:59 +0000)]
[ExecutionEngine] Remove cruft and fix a couple of warnings in the test case for
r241962.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241973
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Tyler Nowicki [Sat, 11 Jul 2015 00:31:11 +0000 (00:31 +0000)]
Renamed some uses of unroll to interleave in the vectorizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241971
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Duncan P. N. Exon Smith [Fri, 10 Jul 2015 23:55:34 +0000 (23:55 +0000)]
MC: Shrink MCDwarfLoc/MCLineEntry
Drop 8 bytes off of `MCDwarfLoc` by restricting the `Isa`, `Column`, and
`Flags` members to appropriate sizes (from `DWARFDebugLine::Row`).
Saves a little over 0.5% off the heap of llc with no real functionality
change.
(I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`;
see r236629 for details.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241970
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Adrian Prantl [Fri, 10 Jul 2015 23:31:08 +0000 (23:31 +0000)]
Clean up the comments in DIBuilder.h to adhere to the coding standards
a little more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241969
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Adrian Prantl [Fri, 10 Jul 2015 23:31:05 +0000 (23:31 +0000)]
Revert "Clean up the comments in DIBuilder.h to adhere to the coding standards"
This reverts commit 241965. (I accidentally committed too much).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241968
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Adrian Prantl [Fri, 10 Jul 2015 23:26:02 +0000 (23:26 +0000)]
Cleanup a couple of comments in DIBuilder.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241966
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Adrian Prantl [Fri, 10 Jul 2015 23:25:54 +0000 (23:25 +0000)]
Clean up the comments in DIBuilder.h to adhere to the coding standards
a little more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241965
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Lang Hames [Fri, 10 Jul 2015 22:56:47 +0000 (22:56 +0000)]
[ExecutionEngine] Use std::function rather than a function pointer for the
LazyFunctionCreator.
Patch by Pierre-Andre Saulais. Thanks Pierre!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241962
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Duncan P. N. Exon Smith [Fri, 10 Jul 2015 22:52:15 +0000 (22:52 +0000)]
MC: Only allow changing feature bits in MCSubtargetInfo
Disallow all mutation of `MCSubtargetInfo` expect the feature bits.
Besides deleting the assignment operators -- which were dead "code" --
this restricts `InitMCProcessorInfo()` to subclass initialization
sequences, and exposes a new more limited function called
`setDefaultFeatures()` for use by the ARMAsmParser `.cpu` directive.
There's a small functional change here: ARMAsmParser used to adjust
`MCSubtargetInfo::CPUSchedModel` as a side effect of calling
`InitMCProcessorInfo()`, but I've removed that suspicious behaviour.
Since the AsmParser shouldn't be doing any scheduling, there shouldn't
be any observable change...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241961
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Matt Arsenault [Fri, 10 Jul 2015 22:51:36 +0000 (22:51 +0000)]
AMDGPU: Fix chains for memory ops dependent on argument loads
Most loads and stores are derived from pointers derived from
a kernel argument load inserted during argument lowering.
This was just using the EntryToken chain for the argument loads,
and any users of these loads were also on the EntryToken chain.
Return the chain of the lowered argument load so that dependent loads
end up on the correct chain.
No test since I'm not aware of any case where this actually
broke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241960
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Alex Lorenz [Fri, 10 Jul 2015 22:51:20 +0000 (22:51 +0000)]
MIR Serialization: Serialize the virtual register operands.
Reviewers: Duncan P. N. Exon Smith
Differential Revision: http://reviews.llvm.org/D11005
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241959
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David Majnemer [Fri, 10 Jul 2015 22:46:02 +0000 (22:46 +0000)]
[IR] Switch static const to an enum to silence MSVC linker warnings
Integral class statics are handled oddly in MSVC, we don't need them
in this case, use an enum instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241958
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Duncan P. N. Exon Smith [Fri, 10 Jul 2015 22:43:42 +0000 (22:43 +0000)]
MC: Remove MCSubtargetInfo() default constructor
Force all creators of `MCSubtargetInfo` to immediately initialize it,
merging the default constructor and the initializer into an initializing
constructor. Besides cleaning up the code a little, this makes it clear
that the initializer is never called again later.
Out-of-tree backends need a trivial change: instead of calling:
auto *X = new MCSubtargetInfo();
InitXYZMCSubtargetInfo(X, ...);
return X;
they should call:
return createXYZMCSubtargetInfoImpl(...);
There's no real functionality change here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241957
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Duncan P. N. Exon Smith [Fri, 10 Jul 2015 22:33:01 +0000 (22:33 +0000)]
MC: Remove MCSubtargetInfo::InitCPUSched()
Remove all calls to `MCSubtargetInfo::InitCPUSched()` and merge its body
into the only relevant caller, `MCSubtargetInfo::InitMCProcessorInfo()`.
We were only calling the former after explicitly calling the latter with
the same CPU; it's confusing to have both methods exposed.
Besides a minor (surely unmeasurable) speedup in ARM and X86 from
avoiding running the logic twice, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241956
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Bjorn Steinbrink [Fri, 10 Jul 2015 22:30:17 +0000 (22:30 +0000)]
[InstCombine] Actually combine AA metadata when replacing one load with another
Fixes PR24083
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241955
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Matt Arsenault [Fri, 10 Jul 2015 22:28:41 +0000 (22:28 +0000)]
AMDGPU: Use requested chain when lowering arguments
No test since I'm not aware of any case where this will
end up being a different chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241954
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Matthias Braun [Fri, 10 Jul 2015 22:23:57 +0000 (22:23 +0000)]
ARM: Use SpecificBumpPtrAllocator to fix leak introduced in r241920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241951
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Reid Kleckner [Fri, 10 Jul 2015 22:21:54 +0000 (22:21 +0000)]
[SEH] Push reloads of the SEH code past phi nodes
This in turn would sometimes introduce new cleanupblocks that didn't
previously exist. The uses were being introduced by SSA value demotion.
We actually want to *promote* uses of EH pointers and selectors, so I
added some spcecial casing to avoid demoting such instructions. This is
getting overly complicated, but hopefully we'll come along and delete it
in the new representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241950
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Duncan P. N. Exon Smith [Fri, 10 Jul 2015 22:17:49 +0000 (22:17 +0000)]
Add <type_traits> for is_pod, fixing r241947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241949
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Matt Arsenault [Fri, 10 Jul 2015 22:17:40 +0000 (22:17 +0000)]
DAGCombiner: Assume invariant load cannot alias a store
The motivation is to allow GatherAllAliases / FindBetterChain
to not give up on dependent loads of a pointer from constant memory.
This is important for AMDGPU, because most loads are pointers
derived from a load of a kernel argument from constant memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241948
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Duncan P. N. Exon Smith [Fri, 10 Jul 2015 22:13:43 +0000 (22:13 +0000)]
MC: Remove the copy of MCSchedModel in MCSubtargetInfo
`MCSchedModel` is large. Make `MCSchedModel::GetDefaultSchedModel()`
return by-reference instead of by-value, so we can store a pointer in
`MCSubtargetInfo::CPUSchedModel` instead of a copy.
Note: since `MCSchedModel` is POD, this doesn't create a static
constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241947
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Quentin Colombet [Fri, 10 Jul 2015 22:09:55 +0000 (22:09 +0000)]
[ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks.
Although this is not incorrect to insert such code, it is useless
and it hurts the binary size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241946
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David Majnemer [Fri, 10 Jul 2015 21:50:04 +0000 (21:50 +0000)]
[MC] Switch static const to an enum to silence MSVC linker warnings
Integral class statics are handled oddly in MSVC, we don't need them in
this case, use an enum instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241945
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Evgeniy Stepanov [Fri, 10 Jul 2015 21:24:07 +0000 (21:24 +0000)]
Fix AArch64 prologue for empty frame with dynamic allocas.
Fixes PR23804: assertion failure in emitPrologue in the case of a
function with an empty frame and a dynamic alloca that needs stack
realignment. This is a typical case for AddressSanitizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241943
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Jingyue Wu [Fri, 10 Jul 2015 21:14:54 +0000 (21:14 +0000)]
[TTI] BasicTTIImpl assumes no vector registers
Summary:
Following the discussion on r241884, it's more reasonable to assume that a
target has no vector registers by default instead of letting every such
target overrides getNumberOfRegisters.
Therefore, this patch modifies BasicTTIImpl::getNumberOfRegisters to
return 0 when Vector is true, and partially reverts r241884 which
modifies NVPTXTTIImpl::getNumberOfRegisters.
It also fixes a performance bug in LoopVectorizer. Even if a target has
no vector registers, vectorization may still help ILP. So, we need both
checks to be false before disabling loop vectorization all together.
Reviewers: hfinkel
Subscribers: llvm-commits, jholewinski
Differential Revision: http://reviews.llvm.org/D11108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241942
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JF Bastien [Fri, 10 Jul 2015 20:24:17 +0000 (20:24 +0000)]
Fix `llvm-config` to emit the linker flag for the combined shared object built by autoconfig/make instead of the individual components.
Summary:
This fixes `llvm-config` instead of fixing the makefiles because, AIUI, LLVM's autoconfig/make build system is on the way out anyway.
This change only affects builds that use autoconfig/make.
Reviewers: jfb
Subscribers: echristo, dschuff, llvm-commits
Differential Revision: http://reviews.llvm.org/D10716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241938
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Michael J. Spencer [Fri, 10 Jul 2015 20:11:57 +0000 (20:11 +0000)]
[Object][ELF] Handle the dynamic string table in files without a section table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241937
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Jan Wen Voung [Fri, 10 Jul 2015 19:46:16 +0000 (19:46 +0000)]
Fix enum BitcodeError to not define a zero-valued error code.
Summary:
std::error_code assumes it isn't an error if the error code is zero.
Patch by Karl Schimpf
Reviewers: rafael
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241933
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Adam Nemet [Fri, 10 Jul 2015 18:55:13 +0000 (18:55 +0000)]
[LoopDist/LoopVer] Move LoopVersioning to a new module, NFC
Summary:
The class will obviously need improvement down the road. For one, there
is no reason that addPHINodes would have to be exposed like that. I
will make this and other improvements in follow-up patches.
The main goal is to be able to share this functionality. The
LoopLoadElimination pass I am working on needs it too. Later we can
move other clients as well (LV and Ashutosh's LICMVer).
Reviewers: hfinkel, ashutosh.nema
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241932
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Adam Nemet [Fri, 10 Jul 2015 18:55:09 +0000 (18:55 +0000)]
[LoopDist] Move loop-versioning helper functions to Cloning, NFC
Summary:
This makes them available to the LoopVersioning class as that is moved
to its own module in the next patch.
Reviewers: ashutosh.nema, hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241931
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Matthias Braun [Fri, 10 Jul 2015 18:37:33 +0000 (18:37 +0000)]
ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code
This commit factors out common code from MergeBaseUpdateLoadStore() and
MergeBaseUpdateLSMultiple() and introduces a new function
MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a
strd/ldrd instruction into an strd/ldrd instruction with writeback where
possible.
Differential Revision: http://reviews.llvm.org/D10676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241928
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Fiona Glaser [Fri, 10 Jul 2015 18:29:02 +0000 (18:29 +0000)]
ComputeKnownBits: be a bit smarter about ADDs
If our two inputs have known top-zero bit counts M and N, we trivially
know that the output cannot have any bits set in the top (min(M, N)-1)
bits, since nothing could carry past that point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241927
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Matthias Braun [Fri, 10 Jul 2015 18:28:49 +0000 (18:28 +0000)]
ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2
Differential Revision: http://reviews.llvm.org/D10623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241926
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JF Bastien [Fri, 10 Jul 2015 18:23:10 +0000 (18:23 +0000)]
WebAssembly: basic instructions todo, and basic register info.
Summary:
This code is based on AArch64 for modern backend good practice, and NVPTX for
virtual ISA concerns.
Reviewers: sunfish
Subscribers: aemerson, llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241923
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Alex Lorenz [Fri, 10 Jul 2015 18:13:57 +0000 (18:13 +0000)]
MIR Serialization: Initial serialization of stack objects.
This commit implements the initial serialization of stack objects from the
MachineFrameInfo class. It can only serialize the ordinary stack objects
(including ordinary spill slots), but it doesn't serialize variable sized or
fixed stack objects yet.
The stack objects are serialized using a YAML sequence of YAML inline mappings.
Each mapping has the object's ID, type, size, offset and alignment. The stack
objects are a part of machine function's YAML mapping.
Reviewers: Duncan P. N. Exon Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241922
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JF Bastien [Fri, 10 Jul 2015 18:13:17 +0000 (18:13 +0000)]
Target RegisterInfo: devirtualize TargetFrameLowering
Summary:
The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can.
This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here.
Subscribers: sunfish, ted, llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11093
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241921
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Matthias Braun [Fri, 10 Jul 2015 18:08:49 +0000 (18:08 +0000)]
ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.
This improves the logic in several ways and is a preparation for
followup patches:
- First perform an analysis and create a list of merge candidates, then
transform. This simplifies the code in that you have don't have to
care to much anymore that you may be holding iterators to
MachineInstrs that get removed.
- Analyze/Transform basic blocks in reverse order. This allows to use
LivePhysRegs to find free registers instead of the RegisterScavenger.
The RegisterScavenger will become less precise in the future as it
relies on the deprecated kill-flags.
- Return the newly created node in MergeOps so there's no need to look
around in the schedule to find it.
- Rename some MBBI iterators to InsertBefore to make their role clear.
- General code cleanup.
Differential Revision: http://reviews.llvm.org/D10140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241920
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Eli Bendersky [Fri, 10 Jul 2015 15:40:33 +0000 (15:40 +0000)]
Actually support volatile memcpys in NVPTX lowering
Differential Revision: http://reviews.llvm.org/D11091
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241914
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Nemanja Ivanovic [Fri, 10 Jul 2015 14:25:17 +0000 (14:25 +0000)]
NFC. Added a blank line for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241913
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Benjamin Kramer [Fri, 10 Jul 2015 14:02:02 +0000 (14:02 +0000)]
[InstSimplify] Fold away ord/uno fcmps when nnan is present.
This is important to fold away the slow case of complex multiplies
emitted by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241911
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James Molloy [Fri, 10 Jul 2015 12:52:00 +0000 (12:52 +0000)]
Add support for fast-math flags to the FCmp instruction.
FCmp behaves a lot like a floating-point binary operator in many ways,
and can benefit from fast-math information. Flags such as nsz and nnan
can affect if this fcmp (in combination with a select) can be treated
as a fminnum/fmaxnum operation.
This adds backwards-compatible bitcode support, IR parsing and writing,
LangRef changes and IRBuilder changes. I'll need to audit InstSimplify
and InstCombine in a followup to find places where flags should be
copied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241901
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Nemanja Ivanovic [Fri, 10 Jul 2015 12:38:08 +0000 (12:38 +0000)]
Add missing builtins to the PPC back end for ABI compliance (vol. 3)
This patch corresponds to review:
http://reviews.llvm.org/D10973
Back end portion of the third round of additions to altivec.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241900
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Alexey Bataev [Fri, 10 Jul 2015 10:37:09 +0000 (10:37 +0000)]
Disable loop re-rotation for -Oz (patch by Andrey Turetsky)
After changes in rL231820 loop re-rotation is performed even in -Oz mode. Since loop rotation is disabled for -Oz, it seems loop re-rotation should be disabled too.
Differential Revision: http://reviews.llvm.org/D10961
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241897
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Pawel Bylica [Fri, 10 Jul 2015 10:01:47 +0000 (10:01 +0000)]
[llvm-stress] Enhance scalar type selection from command line.
llvm-stress command line options like -generate-x86-fp80 has been replaced with one list-like option -types. E.g. llvm-stress -types=x86_fp80,i100,i256,half. Default types (i1, i8, i16, i32, i64, float, double) are always added at the beginning of that list.
Reviewers: hfinkel
Differential Revision: http://reviews.llvm.org/D10667
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241896
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NAKAMURA Takumi [Fri, 10 Jul 2015 08:43:41 +0000 (08:43 +0000)]
llvm/Object/ELF.h: Appease g++-4.7.2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241895
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David Majnemer [Fri, 10 Jul 2015 07:15:17 +0000 (07:15 +0000)]
Revert the new EH instructions
This reverts commits r241888-r241891, I didn't mean to commit them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241893
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Daniel Jasper [Fri, 10 Jul 2015 07:09:20 +0000 (07:09 +0000)]
Add missing 'const'. I don't think this is strictly required, but some
compiler configuration is giving me an error and it seems to be
recommended anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241892
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David Majnemer [Fri, 10 Jul 2015 07:01:07 +0000 (07:01 +0000)]
Tighten the verifier check for catchblock.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241891
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David Majnemer [Fri, 10 Jul 2015 07:01:03 +0000 (07:01 +0000)]
Address Joseph's review comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241890
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David Majnemer [Fri, 10 Jul 2015 07:00:58 +0000 (07:00 +0000)]
Address Reid's review feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241889
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David Majnemer [Fri, 10 Jul 2015 07:00:44 +0000 (07:00 +0000)]
New EH representation for MSVC compatibility
Summary:
This introduces new instructions neccessary to implement MSVC-compatible
exception handling support. Most of the middle-end and none of the
back-end haven't been audited or updated to take them into account.
Reviewers: rnk, JosephTremoulet, reames, nlewycky, rjmccall
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241888
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Bjorn Steinbrink [Fri, 10 Jul 2015 06:55:49 +0000 (06:55 +0000)]
[InstCombine] Employ AliasAnalysis in FindAvailableLoadedValue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241887
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Bjorn Steinbrink [Fri, 10 Jul 2015 06:55:44 +0000 (06:55 +0000)]
[InstCombine] Properly combine metadata when replacing a load with another
Not doing this can lead to misoptimizations down the line, e.g. because
of range metadata on the replacing load excluding values that are valid
for the load that is being replaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241886
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Jingyue Wu [Fri, 10 Jul 2015 04:31:56 +0000 (04:31 +0000)]
[NVPTX] declare no vector registers
Summary:
Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll)
produces code with complex control flow which hurts later optimizations. Since
NVPTX doesn't have vector registers in LLVM's sense
(NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector
registers to effectively disable loop vectorization.
Reviewers: jholewinski
Subscribers: jingyue, llvm-commits, jholewinski
Differential Revision: http://reviews.llvm.org/D11089
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241884
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Reid Kleckner [Fri, 10 Jul 2015 00:08:49 +0000 (00:08 +0000)]
[WinEH] Make sure LSDA tables are 4 byte aligned
Apparently this is important, otherwise _except_handler3 assumes that
the registration node is corrupted and ignores it.
Also fix a bug in WinEHPrepare where we would insert code after a
terminator instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241877
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Eli Bendersky [Thu, 9 Jul 2015 23:06:03 +0000 (23:06 +0000)]
Replace index-loops by range-based loops
NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241875
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Sanjay Patel [Thu, 9 Jul 2015 22:58:39 +0000 (22:58 +0000)]
[x86] enable machine combiner reassociations for scalar double-precision multiplies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241873
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Sanjay Patel [Thu, 9 Jul 2015 22:48:54 +0000 (22:48 +0000)]
[x86] enable machine combiner reassociations for scalar double-precision adds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241871
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Michael J. Spencer [Thu, 9 Jul 2015 22:42:21 +0000 (22:42 +0000)]
Fix shadowing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241870
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Michael J. Spencer [Thu, 9 Jul 2015 22:32:24 +0000 (22:32 +0000)]
[Object][ELF] Support dumping hash-tables from files with no section table.
This time without breaking the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241869
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Alex Lorenz [Thu, 9 Jul 2015 22:23:13 +0000 (22:23 +0000)]
MIR Serialization: Serialize the virtual register definitions.
The virtual registers are serialized using a YAML sequence of YAML inline
mappings. Each mapping has the id of the virtual register and the register
class.
Reviewers: Duncan P. N. Exon Smith
Differential Revision: http://reviews.llvm.org/D10981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241868
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Adam Nemet [Thu, 9 Jul 2015 22:17:41 +0000 (22:17 +0000)]
[LAA] Fix grammar in debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241867
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Adam Nemet [Thu, 9 Jul 2015 22:17:38 +0000 (22:17 +0000)]
[LAA] Hide NeedRTCheck logic completely inside canCheckPtrAtRT, NFC
Currently canCheckPtrAtRT returns two flags NeedRTCheck and CanDoRT.
NeedRTCheck says whether we need checks and CanDoRT whether we can
generate the checks. The idea is to encode three states with these:
Need/Can:
(1) false/dont-care: no checks are needed
(2) true/false: we need checks but can't generate them
(3) true/true: we need checks and we can generate them
This is pretty unnecessary since the caller (analyzeLoop) is only
interested in whether we can generate the checks if we actually need
them (i.e. 1 or 3).
So this change cleans up to return just that (CanDoRTIfNeeded) and pulls
all the underlying logic into canCheckPtrAtRT.
By doing all this, we simplify analyzeLoop which is the complex function
in LAA.
There is further room for improvement here by using RtCheck.Need
directly rather than a new local variable NeedRTCheck but that's for a
later patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241866
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Reid Kleckner [Thu, 9 Jul 2015 22:09:41 +0000 (22:09 +0000)]
[WinEH] Give up on using CSRs across 32-bit invokes for now
The runtime does not restore CSRs when transferring control back to the
function handling the exception. According to the experts on IRC, LLVM's
register allocator has no way to model register clobbers that only
happen on one edge of the CFG. For now, don't worry about trying to use
the meager three CSRs available on 32-bit X86 and just say that such
invokes preserve nothing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241865
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Reid Kleckner [Thu, 9 Jul 2015 21:48:40 +0000 (21:48 +0000)]
Expose sjlj preparation through opt for my own debugging purposes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241864
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Alex Lorenz [Thu, 9 Jul 2015 21:21:33 +0000 (21:21 +0000)]
MIR Parser: Report an error when parsing machine function with an empty body.
This commit adds a new error which is reported when the MIR Parser encounters
a machine function without any machine basic blocks. The machine verifier
expects that the machine functions have at least one MBB, and this error will
prevent machine functions without MBBs from reaching the machine verifier and
crashing with an assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241862
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Tom Stellard [Thu, 9 Jul 2015 21:20:37 +0000 (21:20 +0000)]
AMDGPU: Add helper function for implicit parameter offsets.
Patch by: Zoltan Gilian
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241861
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JF Bastien [Thu, 9 Jul 2015 21:00:09 +0000 (21:00 +0000)]
Unbreak WebAssembly build
Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed.
Reviewers: sunfish, joker.eph, echristo
Subscribers: llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241859
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JF Bastien [Thu, 9 Jul 2015 20:57:38 +0000 (20:57 +0000)]
WebAssembly: add placeholder intrinsics header
Reviewers: sunfish
Subscribers: llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241858
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Sanjoy Das [Thu, 9 Jul 2015 20:13:31 +0000 (20:13 +0000)]
[ImplicitNullChecks] Fix a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241851
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Sanjoy Das [Thu, 9 Jul 2015 20:13:25 +0000 (20:13 +0000)]
[ImplicitNullChecks] Be smarter in picking the memory op.
Summary:
Before this change ImplicitNullChecks would only pick loads of the form:
```
test Reg, Reg
jz elsewhere
fallthrough:
movl 32(Reg), Reg2
```
but not (say)
```
test Reg, Reg
jz elsewhere
fallthrough:
inc Reg3
movl 32(Reg), Reg2
```
This change teaches ImplicitNullChecks to look through "unrelated"
instructions like `inc Reg3` when searching for a load instruction
to convert to a trapping load.
Reviewers: atrick, JosephTremoulet, reames
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241850
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Rafael Espindola [Thu, 9 Jul 2015 20:12:50 +0000 (20:12 +0000)]
Create BSD archives by default on OS X.
They should probably be created on anything that is not windows or linux, but I will
test on freebsd before changing that.
With this it is possible to bootstrap with llvm-ar instead of ar+ranlib on OS X.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241849
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Alex Lorenz [Thu, 9 Jul 2015 19:55:27 +0000 (19:55 +0000)]
MIR Serialization: Serialize the simple MachineFrameInfo attributes.
This commit serializes the 13 scalar boolean and integer attributes from the
MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap,
HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack,
HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and
HasMustTailInVarArgFunc. These attributes are serialized as part
of the frameInfo YAML mapping, which itself is a part of the machine function's
YAML mapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241844
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Rafael Espindola [Thu, 9 Jul 2015 19:48:06 +0000 (19:48 +0000)]
llvm-ar: Pad the symbol table to 4 bytes.
It looks like ld64 requires it. With this we seem to be able to bootstrap using
llvm-ar+/usr/bin/true instead of ar+ranlib (currently on stage2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241842
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Matt Arsenault [Thu, 9 Jul 2015 18:47:03 +0000 (18:47 +0000)]
AMDGPU/R600: Return correct chain when lowering loads
The other LowerLOAD should be returning the correct chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241839
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Sanjoy Das [Thu, 9 Jul 2015 18:46:12 +0000 (18:46 +0000)]
[IndVars] Try to use existing values in RewriteLoopExitValues.
Summary:
In RewriteLoopExitValues, before expanding out an SCEV expression using
SCEVExpander, try to see if an existing LLVM IR expression already
computes the value we're interested in. If so use that existing
expression.
Apart from reducing IndVars' reliance on the rest of the compilation
pipeline, this also prevents IndVars from concluding some expressions as
"high cost" when they're not. For instance,
`InductiveRangeCheckElimination` often emits code of the following form:
```
len = umin(len_A, len_B)
loop:
...
if (i++ < len)
goto loop
outside_loop:
use(i)
```
`SCEVExpander` refuses to rewrite the use of `i` in `outside_loop`,
since it thinks the value of `i` on loop exit, `len`, is a high cost
expansion since it contains an `umax` in it. With this change,
`IndVars` can see that it can re-use `len` instead of creating a new
expression to compute `umin(len_A, len_B)`.
I considered putting this cleverness in `SCEVExpander`, but I was
worried that it may then have a deterimental effect on other passes
that use it. So I decided it was better to just do this in the one
place where it seems like an obviously good idea, with the intent of
generalizing later if needed.
Reviewers: atrick, reames
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241838
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Simon Atanasyan [Thu, 9 Jul 2015 18:23:10 +0000 (18:23 +0000)]
[llvm-readobj] Print MIPS PLT table
Now the -mips-plt-got prints both MIPS GOT and PLT tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241836
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Simon Atanasyan [Thu, 9 Jul 2015 18:23:02 +0000 (18:23 +0000)]
[yaml2obj] Initialize sh_addralign field for the .symtab section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241835
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Simon Atanasyan [Thu, 9 Jul 2015 18:22:55 +0000 (18:22 +0000)]
[ELF] Explicitly configure sections alignment in the tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241834
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David Majnemer [Thu, 9 Jul 2015 18:14:31 +0000 (18:14 +0000)]
[llvm-readobj] Re-add sanity checking which was accidentally removed in r241764
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241831
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David Majnemer [Thu, 9 Jul 2015 18:11:40 +0000 (18:11 +0000)]
[llvm-objdump] Require that jump targets shown in -d are functions
Don't let the disassembler pick call <.text> if a function happens to
live at the start of the section by only using function symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241830
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Reid Kleckner [Thu, 9 Jul 2015 17:46:39 +0000 (17:46 +0000)]
Remove dead code from old 64-bit SEH lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241829
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Pat Gavlin [Thu, 9 Jul 2015 17:40:29 +0000 (17:40 +0000)]
Allow {e,r}bp as the target of {read,write}_register.
This patch allows the read_register and write_register intrinsics to
read/write the RBP/EBP registers on X86 iff the targeted register is
the frame pointer for the containing function.
Differential Revision: http://reviews.llvm.org/D10977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241827
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Sanjay Patel [Thu, 9 Jul 2015 17:28:37 +0000 (17:28 +0000)]
fix an invisible bug when combining repeated FP divisors
This patch fixes bugs that were exposed by the addition of fast-math-flags in the DAG:
r237046 ( http://reviews.llvm.org/rL237046 ):
1. When replacing a division node, it's not enough to RAUW.
We should call CombineTo() to delete dead nodes and combine again.
2. Because we are changing the DAG, we can't return an empty SDValue
after the transform. As the code comments say:
Visitation implementation - Implement dag node combining for different node types.
The semantics are as follows: Return Value:
SDValue.getNode() == 0 - No change was made
SDValue.getNode() == N - N was replaced, is dead and has been handled.
otherwise - N should be replaced by the returned Operand.
The new test case shows no difference with or without this patch, but it will crash if
we re-apply r237046 or enable FMF via the current -enable-fmf-dag cl::opt.
Differential Revision: http://reviews.llvm.org/D9893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241826
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Juergen Ributzka [Thu, 9 Jul 2015 17:11:15 +0000 (17:11 +0000)]
[StackMap] Use lambdas to specify the sort and erase conditions. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241823
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Juergen Ributzka [Thu, 9 Jul 2015 17:11:11 +0000 (17:11 +0000)]
[StackMap] Rename variables to be more consistent. NFC.
Rename a few variables and use auto for long iterator names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241822
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Juergen Ributzka [Thu, 9 Jul 2015 17:11:08 +0000 (17:11 +0000)]
[StackMaps] Use emplace_back when possible. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241821
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Silviu Baranga [Thu, 9 Jul 2015 16:40:25 +0000 (16:40 +0000)]
Add a test of a regression discovered during testing of r241673
Summary:
We were missing a corner case where DepCands was not available,
but we were using DepCands to compute the checking pointer
groups.
This adds a test for that regression.
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241818
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Tom Stellard [Thu, 9 Jul 2015 16:30:36 +0000 (16:30 +0000)]
AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one use
This is convered by existing testcases and will be exposed by a future
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241817
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Tom Stellard [Thu, 9 Jul 2015 16:30:27 +0000 (16:30 +0000)]
AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()
No test case for this. I ran into it while working on some improvements
to SIShrinkInstructions.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241816
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Rafael Espindola [Thu, 9 Jul 2015 15:58:22 +0000 (15:58 +0000)]
Add missing file from previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241815
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Rafael Espindola [Thu, 9 Jul 2015 15:56:23 +0000 (15:56 +0000)]
Basic support for BSD symbol tables in archives.
This could be optimized and for now we only produce __.SYMDEF
and not "__.SYMDEF SORTED".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241814
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Krzysztof Parzyszek [Thu, 9 Jul 2015 15:40:25 +0000 (15:40 +0000)]
[Hexagon] Add missing preamble to a source file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241813
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Rafael Espindola [Thu, 9 Jul 2015 15:24:39 +0000 (15:24 +0000)]
Remove redundant variable. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241810
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Silviu Baranga [Thu, 9 Jul 2015 15:18:25 +0000 (15:18 +0000)]
Don't rely on the DepCands iteration order when constructing checking pointer groups
Summary:
The checking pointer group construction algorithm relied on the iteration on DepCands.
We would need the same leaders across runs and the same iteration order over the underlying std::set for determinism.
This changes the algorithm to process the pointers in the order in which they were added to the runtime check, which is deterministic.
We need to update the tests, since the order in which pointers appear has changed.
No new tests were added, since it is impossible to test for non-determinism.
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241809
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Rafael Espindola [Thu, 9 Jul 2015 15:13:41 +0000 (15:13 +0000)]
Add a helper to printing BE of LE depending on the format.
The gnu ar format uses BE numbers. The BSD one uses LE. Add a helper for one or the
other. NFC for now, just removes some noise from the following patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241808
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Mehdi Amini [Thu, 9 Jul 2015 15:12:23 +0000 (15:12 +0000)]
Re-instate the EVT parameter to getScalarShiftAmountTy() for OOT user
A documentation for this function would be nice by the way.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241807
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Pawel Bylica [Thu, 9 Jul 2015 14:58:04 +0000 (14:58 +0000)]
Reapply fixed r241790: Fix shift legalization and lowering for big constants.
Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt.
Reviewers: nadav, majnemer, sanjoy, RKSimon
Subscribers: RKSimon, llvm-commits
Differential Revision: http://reviews.llvm.org/D10767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241806
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