Remove isTwoAddress from Blackfin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106457 91177308-0d34-0410-b5e6-96231b3b80d8

Remove isTwoAddress from MSP430.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106455 91177308-0d34-0410-b5e6-96231b3b80d8

Make this test more robust in case LLVM ever decides to align the global
variable differently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106454 91177308-0d34-0410-b5e6-96231b3b80d8

Use A.append(...) instead of A.insert(A.end(), ...) when A is a
SmallVector, and other SmallVector simplifications.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106452 91177308-0d34-0410-b5e6-96231b3b80d8

Make 80-column.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106448 91177308-0d34-0410-b5e6-96231b3b80d8

Remove isTwoAddress from PIC16.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106447 91177308-0d34-0410-b5e6-96231b3b80d8

Remove isTwoAddress from XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106446 91177308-0d34-0410-b5e6-96231b3b80d8

Remove isTwoAddress from Alpha.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106445 91177308-0d34-0410-b5e6-96231b3b80d8

Move several non-performance-critical member functinos out of line.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106444 91177308-0d34-0410-b5e6-96231b3b80d8

Add missing FileCheck call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106443 91177308-0d34-0410-b5e6-96231b3b80d8

test case for r106438.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106439 91177308-0d34-0410-b5e6-96231b3b80d8

Do not directly use function names to construct new name for named metadata.
"llvm.dbg.lv.~A" is not a valid name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106438 91177308-0d34-0410-b5e6-96231b3b80d8

Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106437 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106436 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR 7433.  Silly typo in non-Darwin ARM tail call
handling, plus correct R9 handling in that mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8

Add some codegen patterns for x86_64-linux-gnu tls codegen matching.

Based on a patch by Patrick Marlier!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106433 91177308-0d34-0410-b5e6-96231b3b80d8

early exit for dbg_value instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106430 91177308-0d34-0410-b5e6-96231b3b80d8

remove some dead variables reported by clang++

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106428 91177308-0d34-0410-b5e6-96231b3b80d8

make the Value constructor protected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106427 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r106422, which is breaking the non-fast-isel path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106423 91177308-0d34-0410-b5e6-96231b3b80d8

More changes for non-top-down fast-isel.

Split the code for materializing a value out of
SelectionDAGBuilder::getValue into a helper function, so that it can
be used in other ways. Add a new getNonRegisterValue function which
uses it, for use in code which doesn't want a CopyFromReg even
when FuncMap.ValueMap already has an entry for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106422 91177308-0d34-0410-b5e6-96231b3b80d8

Add the check to the testcase of r106419.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106421 91177308-0d34-0410-b5e6-96231b3b80d8

Mark the SPU 'lr' instruction to never have side effects.
This allows the fast regiser allocator to remove redundant
register moves.
Update a set of tests that depend on the register allocator
to be linear scan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106419 91177308-0d34-0410-b5e6-96231b3b80d8

Do one lookup instead of two.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106415 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize this to look in the regular ValueMap in addition to
the LocalValueMap, to make it more flexible when fast-isel isn't
proceding straight top-down.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106414 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch.

I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106413 91177308-0d34-0410-b5e6-96231b3b80d8

Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm
used to choke llc with the attached test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106411 91177308-0d34-0410-b5e6-96231b3b80d8

add_input_file and add_input_library now take const arguments, remove the
const_cast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106410 91177308-0d34-0410-b5e6-96231b3b80d8

Save more temps with -save-temps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106409 91177308-0d34-0410-b5e6-96231b3b80d8

wip

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106408 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for returning multiple vectors via sret, which is how the ARM target expects the intrinsics to work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106406 91177308-0d34-0410-b5e6-96231b3b80d8

Fix warning in no-asserts build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106405 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a crash caused by dereference of MBB.end(). rdar://8110842

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106399 91177308-0d34-0410-b5e6-96231b3b80d8

Restore a call to rememberInstruction which was accidentally dropped
in refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106398 91177308-0d34-0410-b5e6-96231b3b80d8

Add a TODO comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106397 91177308-0d34-0410-b5e6-96231b3b80d8

Include the use kind along with the expression in the key of the
use sharing map. The reconcileNewOffset logic already forces a
separate use if the kinds differ, so incorporating the kind in the
key means we can track more sharing opportunities.

More sharing means fewer total uses to track, which means smaller
problem sizes, which means the conservative throttles don't kick
in as often.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106396 91177308-0d34-0410-b5e6-96231b3b80d8

Don't include things in anonymous namespaces that don't need it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106395 91177308-0d34-0410-b5e6-96231b3b80d8

Use calloc instead of new/memset, it is more efficient when the set is very large.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106390 91177308-0d34-0410-b5e6-96231b3b80d8

Fix ScalarEvolution's "exhaustive" trip count evaluation code to avoid
assuming that loops are in canonical form, as ScalarEvolution doesn't
depend on LoopSimplify itself. Also, with indirectbr not all loops can
be simplified. This fixes PR7416.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106389 91177308-0d34-0410-b5e6-96231b3b80d8

Factor out duplicated code for reusing and inserting casts into
a helper function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106388 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106383 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a fixme comment that is no longer relevant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106382 91177308-0d34-0410-b5e6-96231b3b80d8

Fix error message to match function name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106381 91177308-0d34-0410-b5e6-96231b3b80d8

Refactoring of regular logical packed instructions to prepare for AVX ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106375 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor aliased packed logical instructions, also add
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8

Ignore dbg_value's.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106373 91177308-0d34-0410-b5e6-96231b3b80d8

Move new sse 1 & 2 generic classes to a more appropriate place

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106372 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unnecessary arguments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106371 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX packed intrinsics for MIN, MAX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106370 91177308-0d34-0410-b5e6-96231b3b80d8

Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8

Finish ripping isTwoAddress out of X86.  Some mindless formatting
and operand renaming to help.

The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106367 91177308-0d34-0410-b5e6-96231b3b80d8

Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106366 91177308-0d34-0410-b5e6-96231b3b80d8

rip out dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106365 91177308-0d34-0410-b5e6-96231b3b80d8

fix rdar://7873482 by teaching the instruction encoder to emit
segment prefixes.  Daniel wrote most of this patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8

Indentation and remove dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106362 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up: remove now unnecessary Constraints

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106361 91177308-0d34-0410-b5e6-96231b3b80d8

Silence compiler warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106360 91177308-0d34-0410-b5e6-96231b3b80d8

more refactoring! yay! big win over the intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106359 91177308-0d34-0410-b5e6-96231b3b80d8

Remove isTwoAddress from here too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106358 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo, SSE1 should be used by XS, not SSE2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106357 91177308-0d34-0410-b5e6-96231b3b80d8

Remove isTwoAddress from 64-bit files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106356 91177308-0d34-0410-b5e6-96231b3b80d8

Move ARM if-conversion before post-ra scheduling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8

Teach regular and fast isel to set dead flags on unused implicit defs
on calls and similar instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8

Apply some refactor to packed instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106349 91177308-0d34-0410-b5e6-96231b3b80d8

Update cmake list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106348 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb2 hazard recognizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106347 91177308-0d34-0410-b5e6-96231b3b80d8

Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean up
the inserted INSERT_SUBREGs after us.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106345 91177308-0d34-0410-b5e6-96231b3b80d8

Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8

back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106342 91177308-0d34-0410-b5e6-96231b3b80d8

Another typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106340 91177308-0d34-0410-b5e6-96231b3b80d8

Enable Expand handling of atomics for subtargets that can't do them inline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106336 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106335 91177308-0d34-0410-b5e6-96231b3b80d8

TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG
instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.

Fix it in LiveVariableAnalysis by adding the <undef> flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106333 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an inverted condition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106330 91177308-0d34-0410-b5e6-96231b3b80d8

Use the new 'defm' class inheritance in SSE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106327 91177308-0d34-0410-b5e6-96231b3b80d8

Fix cross initialization compilation error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106324 91177308-0d34-0410-b5e6-96231b3b80d8

Teach iff-converter to properly count # of dups. It was not skipping over dbg_value's which resulted in non-duplicated instructions being deleted. rdar://8104384.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106323 91177308-0d34-0410-b5e6-96231b3b80d8

Add Expand-to-libcall support for additional atomics. This covers the usual
entries used by llvm-gcc. *_[U]MIN and such can be added later if needed.

This enables the front ends to simplify handling of the atomic intrinsics by
removing the target-specific decision about which targets can handle the
intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106321 91177308-0d34-0410-b5e6-96231b3b80d8

Rewrite chained if's as switches and replace assertions with llvm_unreachable
(as suggested in radar 8104405).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106318 91177308-0d34-0410-b5e6-96231b3b80d8

Fix ARM/Thumb reversal in previous attempt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106314 91177308-0d34-0410-b5e6-96231b3b80d8

When using ADDri to get the address of a stack object, 255 is a conservative
limit on the offset that can be materialized without using the register
scavenger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8

Make this comment less specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106311 91177308-0d34-0410-b5e6-96231b3b80d8

Fix X86FastISel's address-mode folding to stay within the
original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106310 91177308-0d34-0410-b5e6-96231b3b80d8

An attempt to fix the problem Anton reported with
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r106304 (105548 and friends), which are the SCEVComplexityCompare
optimizations. There is still some nondeterminism remaining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106306 91177308-0d34-0410-b5e6-96231b3b80d8

Teach tablegen how to inherit from classes in 'defm' definitions.
The rule is simple: only inherit from a class list if they come
in the end, after the last multiclass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106305 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply 105540, 105542, and 105548, and revert r105732.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106304 91177308-0d34-0410-b5e6-96231b3b80d8

Add a pass-through option to the plugin. The use case for this option is to
ask the linker to take another look into some library or object. The case when
one might want to do this is when codegen introduces a new undefined reference.
The canonical example is libgcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106303 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply 105546.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106302 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply 105544.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106301 91177308-0d34-0410-b5e6-96231b3b80d8

Add explicit keywords.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106300 91177308-0d34-0410-b5e6-96231b3b80d8

Enable tail calls on ARM by default, with some
basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8

Don't leak RegClass2VRegMap, which is now a new[] array instead of a
std::vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106298 91177308-0d34-0410-b5e6-96231b3b80d8

Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8

Last round of changes for ARM tail calls.
Not turning them on yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106295 91177308-0d34-0410-b5e6-96231b3b80d8

Grammar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106292 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR7372: Conditional branches (at least on ARM) are treated as predicated,
so when IfConverter::CopyAndPredicateBlock checks to see if it should ignore
an instruction because it is a branch, it should not check if the branch is
predicated.

This case (when IgnoreBr is true) is only relevant from IfConvertTriangle,
where new branches are inserted after the block has been copied and predicated.
If the original branch is not removed, we end up with multiple conditional
branches (possibly conflicting) at the end of the block.  Aside from any
immediate errors resulting from that, this confuses the AnalyzeBranch functions
so that the branches are not analyzable.  That in turn causes the IfConverter to
think that the "Simple" pattern can be applied, and things go downhill fast
because the "Simple" pattern does _not_ apply if the block can fall through.

This is pretty fragile.  If there are other degenerate cases where AnalyzeBranch
fails, but where the block may still fall through, the IfConverter should not
perform its "Simple" if-conversion.  But, I don't know how to do that with the
current AnalyzeBranch interface, so for now, the best thing seems to be to
avoid creating branches that AnalyzeBranch cannot handle.

Evan, please review!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106291 91177308-0d34-0410-b5e6-96231b3b80d8

Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8

Don't bother calling releaseMemory before destroying the DominatorTreeBase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106287 91177308-0d34-0410-b5e6-96231b3b80d8