oota-llvm.git
9 years ago[NVPTX] Emits "generic()" depending on the original address space
Jingyue Wu [Fri, 24 Apr 2015 02:57:30 +0000 (02:57 +0000)]
[NVPTX] Emits "generic()" depending on the original address space

Summary:
Fixes a bug in the NVPTX codegen. The code used to miss necessary "generic()"
on aggregates of addrspacecasts.

Test Plan: addrspacecast-gvar.ll

Reviewers: eliben, jholewinski

Reviewed By: jholewinski

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D9130

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235689 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[NVPTX] enable NaryReassociate in NVPTX
Jingyue Wu [Fri, 24 Apr 2015 02:54:06 +0000 (02:54 +0000)]
[NVPTX] enable NaryReassociate in NVPTX

Summary:
We run NaryReassociate right after SLSR because SLSR enables many
opportunities for NaryReassociate. For example, in nary-slsr.ll

  foo((a + b) + c);
  foo((a + b * 2) + c);
  foo((a + b * 3) + c);   // 2 muls and 6 adds

after SLSR:

  ab = a + b;
  foo(ab + c);
  ab2 = ab + b;
  foo(ab2 + c);
  ab3 = ab2 + b;
  foo(ab3 + c);           // 6 adds

after NaryReassociate:

  abc = (a + b) + c;
  foo(abc);
  ab2c = abc + b;
  foo(ab2c);
  ab3c = ab2c + b;
  foo(ab3c);              // 4 adds

Test Plan: nary-slsr.ll

Reviewers: jholewinski, eliben

Reviewed By: eliben

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D9066

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235688 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Fix verifier error when producing v_madmk_f32
Matt Arsenault [Fri, 24 Apr 2015 01:57:58 +0000 (01:57 +0000)]
R600/SI: Fix verifier error when producing v_madmk_f32

Copy the kill flags when swapping the operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235687 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoImprove isTriviallyReMaterializable() documentation.
Matthias Braun [Fri, 24 Apr 2015 01:15:27 +0000 (01:15 +0000)]
Improve isTriviallyReMaterializable() documentation.

This should make it clear under which narrow circumstances implicit
physreg uses are okay when rematerializing and prevent people from
accidentally allowing too much when overriding
isReallyTriviallyReMaterializable() even with the weaker assert in the
RegisterCoalescer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235679 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/RegisterCoalescer: Enable more rematerialization/add missing testcase
Matthias Braun [Fri, 24 Apr 2015 00:25:50 +0000 (00:25 +0000)]
R600/RegisterCoalescer: Enable more rematerialization/add missing testcase

This enables the rematerialization of some R600 MOV instructions in the
RegisterCoalescer and adds a testcase for r235668.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235675 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix a couple of typos in comments.
Michael Zolotukhin [Fri, 24 Apr 2015 00:10:27 +0000 (00:10 +0000)]
Fix a couple of typos in comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235674 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRegisterCoalescer: implicit phsreg uses are fine when rematerializing
Matthias Braun [Fri, 24 Apr 2015 00:01:37 +0000 (00:01 +0000)]
RegisterCoalescer: implicit phsreg uses are fine when rematerializing

The target hooks should have already checked them. This change is
necessary to enable the remateriailzation on R600.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235673 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert accidentally committed "MC: Allow targets to stop symbol name quoting"
Matt Arsenault [Thu, 23 Apr 2015 23:34:51 +0000 (23:34 +0000)]
Revert accidentally committed "MC: Allow targets to stop symbol name quoting"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235672 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Special case v_mov_b32 as really rematerializable
Matt Arsenault [Thu, 23 Apr 2015 23:34:48 +0000 (23:34 +0000)]
R600/SI: Special case v_mov_b32 as really rematerializable

This should be fixed to properly understand all rematerializable
instructions while ignoring implicit reads of exec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235671 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMC: Allow targets to stop symbol name quoting
Matt Arsenault [Thu, 23 Apr 2015 23:34:05 +0000 (23:34 +0000)]
MC: Allow targets to stop symbol name quoting

Currently symbol names are printed in quotes if it contains something
outside of the arbitrary set of characters that isAcceptableChar tests
for. On somem targets, it is never OK to print a symbol name in quotes
so allow targets to opt out of this behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235670 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRegisterCoalescer: Avoid unnecessary register class widening for some rematerializations
Matthias Braun [Thu, 23 Apr 2015 23:24:36 +0000 (23:24 +0000)]
RegisterCoalescer: Avoid unnecessary register class widening for some rematerializations

I couldn't provide a testcase as none of the public targets has wide
register classes with alot of subregisters and at the same time an
instruction which "ReMaterializable" and "AsCheapAsAMove" (could
probably be added for R600).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235668 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRe-commit "[SEH] Remove the old __C_specific_handler code now that WinEHPrepare works"
Reid Kleckner [Thu, 23 Apr 2015 23:22:33 +0000 (23:22 +0000)]
Re-commit "[SEH] Remove the old __C_specific_handler code now that WinEHPrepare works"

This reverts commit r235617.

r235649 should have addressed the problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235667 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix modules build post-r235612.
Richard Smith [Thu, 23 Apr 2015 23:22:26 +0000 (23:22 +0000)]
Fix modules build post-r235612.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235666 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Support register name prefixes for vector registers
Hal Finkel [Thu, 23 Apr 2015 23:16:22 +0000 (23:16 +0000)]
[PowerPC] Support register name prefixes for vector registers

Match binutils by supporting the optional register name prefix for new vector
registers ("vs" for VSX registers and "q" for QPX registers).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235665 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Use sync inst alias when printing
Hal Finkel [Thu, 23 Apr 2015 23:05:08 +0000 (23:05 +0000)]
[PowerPC] Use sync inst alias when printing

So long as the choice between printing msync and sync is not ambiguous, we can
print 'sync 0' and just 'sync'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235663 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600: Correctly lower CONCAT_VECTOR nodes with more than 2 operands
Tom Stellard [Thu, 23 Apr 2015 22:59:24 +0000 (22:59 +0000)]
R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operands

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235662 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix comment for NoCommonBits.
Michael Zolotukhin [Thu, 23 Apr 2015 22:55:48 +0000 (22:55 +0000)]
Fix comment for NoCommonBits.

Maybe there is a better wording, but at least it should be technically
correct now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235660 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Add asm/disasm support for dcbt with hint
Hal Finkel [Thu, 23 Apr 2015 22:47:57 +0000 (22:47 +0000)]
[PowerPC] Add asm/disasm support for dcbt with hint

Add assembler/disassembler support for dcbt/dcbtst (and aliases) with the hint
field specified (non-zero). Unforunately, the syntax for this instruction is
special in that it differs for server vs. embedded cores:
   dcbt ra, rb, th [server]
   dcbt th, ra, rb [embedded]
where th can be omitted when it is 0. dcbtst is the same. Thus we need to play
games in the parser and the printer to flip the operands around on the embedded
cores. We'll use the server syntax as the default (binutils currently uses the
embedded form by default, but IBM is changing that).

We also stop marking dcbtst as having unmodeled side effects (this is not
necessary, it is just a hint like dcbt -- noticed by inspection, so no separate
test case).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235657 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Ignore filter clauses while mapping landing pad blocks.
Andrew Kaylor [Thu, 23 Apr 2015 22:38:36 +0000 (22:38 +0000)]
[WinEH] Ignore filter clauses while mapping landing pad blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235656 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove trivial assert to fix NDEBUG Werror builds
Reid Kleckner [Thu, 23 Apr 2015 21:36:32 +0000 (21:36 +0000)]
Remove trivial assert to fix NDEBUG Werror builds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235652 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRecommit r235458: [opaque pointer type] Avoid using PointerType::getElementType for...
David Blaikie [Thu, 23 Apr 2015 21:36:23 +0000 (21:36 +0000)]
Recommit r235458: [opaque pointer type] Avoid using PointerType::getElementType for a few cases of CallInst

(reverted in r235533)

Original commit message:

"Calls to llvm::Value::mutateType are becoming extra-sensitive now that
instructions have extra type information that will not be derived from
operands or result type (alloca, gep, load, call/invoke, etc... ). The
special-handling for mutateType will get more complicated as this work
continues - it might be worth making mutateType virtual & pushing the
complexity down into the classes that need special handling. But with
only two significant uses of mutateType (vectorization and linking) this
seems OK for now.

Totally open to ideas/suggestions/improvements, of course.

With this, and a bunch of exceptions, we can roundtrip an indirect call
site through bitcode and IR. (a direct call site is actually trickier...
I haven't figured out how to deal with the IR deserializer's lazy
construction of Function/GlobalVariable decl's based on the type of the
entity which means looking through the "pointer to T" type referring to
the global)"

The remapping done in ValueMapper for LTO was insufficient as the types
weren't correctly mapped (though I was using the post-mapped operands,
some of those operands might not have been mapped yet so the type
wouldn't be post-mapped yet). Instead use the pre-mapped type and
explicitly map all the types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235651 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Replace more lpad value uses with undef
Reid Kleckner [Thu, 23 Apr 2015 21:22:30 +0000 (21:22 +0000)]
[WinEH] Replace more lpad value uses with undef

We were asserting on code like this:
  extern "C" unsigned long _exception_code();
  void might_crash(unsigned long);
  void foo() {
    __try {
      might_crash(0);
    } __except(1) {
      might_crash(_exception_code());
    }
  }

Gtest and many other libraries get the exception code from the __except
block. What's supposed to happen here is that EAX is live into the
__except block, and it contains the exception code. Eventually we'll
represent that as a use of the landingpad ehptr value, but for now we
can replace it with undef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235649 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[MachineCopyPropagation] Handle undef flags conservatively so that we do not
Quentin Colombet [Thu, 23 Apr 2015 21:17:39 +0000 (21:17 +0000)]
[MachineCopyPropagation] Handle undef flags conservatively so that we do not
remove copies that are useful after breaking some hardware dependencies.
In other words, handle this kind of situations conservatively by assuming reg2
is redefined by the undef flag.
reg1 = copy reg2
= inst reg2<undef>
reg2 = copy reg1
Copy propagation used to remove the last copy.
This is incorrect because the undef flag on reg2 in inst, allows next
passes to put whatever trashed value in reg2 that may help.
In practice we end up with this code:
reg1 = copy reg2
reg2 = 0
= inst reg2<undef>
reg2 = copy reg1

This fixes PR21743.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235647 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUnbreak build
Krzysztof Parzyszek [Thu, 23 Apr 2015 20:57:39 +0000 (20:57 +0000)]
Unbreak build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235646 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Minor cleanup in HexagonFrameLowering
Krzysztof Parzyszek [Thu, 23 Apr 2015 20:42:20 +0000 (20:42 +0000)]
[Hexagon] Minor cleanup in HexagonFrameLowering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235645 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Fix indirect addressing with a negative constant offset
Tom Stellard [Thu, 23 Apr 2015 20:32:01 +0000 (20:32 +0000)]
R600/SI: Fix indirect addressing with a negative constant offset

When the base register index of the vector plus the constant offset
was less than zero, we were passing the wrong base register to the indirect
addressing instruction.

In this case, we need to set the base register to v0 and then add
the computed (negative) index to m0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235641 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoThumb2: When applying branch optimizations, visit branches in reverse order.
Peter Collingbourne [Thu, 23 Apr 2015 20:31:35 +0000 (20:31 +0000)]
Thumb2: When applying branch optimizations, visit branches in reverse order.

The order in which branches appear in ImmBranches is approximately their
order within the function body. By visiting later branches first, we reduce
the distance between earlier forward branches and their targets, making it
more likely that the cbn?z optimization, which can only apply to forward
branches, will succeed for those earlier branches.

Differential Revision: http://reviews.llvm.org/D9185

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235640 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoARM: When re-creating a branch via InsertBranch, preserve CPSR flags.
Peter Collingbourne [Thu, 23 Apr 2015 20:31:32 +0000 (20:31 +0000)]
ARM: When re-creating a branch via InsertBranch, preserve CPSR flags.

In particular, this preserves the kill flag, which allows the Thumb2 cbn?z
optimization to be applied in cases where a branch has been re-created after
the live variables analysis pass, e.g. by the machine block placement pass.

This appears to be low risk; a number of other targets seem to already be
doing something similar, e.g. AArch64, PowerPC.

Differential Revision: http://reviews.llvm.org/D9184

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235639 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoThumb2: When optimizing for size, do not if-convert branches involving comparisons...
Peter Collingbourne [Thu, 23 Apr 2015 20:31:30 +0000 (20:31 +0000)]
Thumb2: When optimizing for size, do not if-convert branches involving comparisons with zero.

This allows the constant island pass to lower these branches to cbn?z
instructions, resulting in a shorter instruction sequence.

Differential Revision: http://reviews.llvm.org/D9183

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235638 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoARM: When spilling extra registers for alignment, prefer low registers on all Thumb...
Peter Collingbourne [Thu, 23 Apr 2015 20:31:26 +0000 (20:31 +0000)]
ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets.

This makes it more likely that we can use the 16-bit push and pop instructions
on Thumb-2, saving around 4 bytes per function.

Differential Revision: http://reviews.llvm.org/D9165

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235637 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoARM: Only enforce 4-byte alignment on Thumb-2 functions with constant pools.
Peter Collingbourne [Thu, 23 Apr 2015 20:31:22 +0000 (20:31 +0000)]
ARM: Only enforce 4-byte alignment on Thumb-2 functions with constant pools.

This appears to have been introduced back in r76698 as part of an unrelated
change. I can find no official ARM documentation stating that Thumb-2 functions
require 4-byte alignment; in fact, ARM documentation appears to contradict
this (see, e.g., ARM Architecture Reference Manual Thumb-2 Supplement,
section 2.6.1: "Thumb-2 enforces 16-bit alignment on all instructions.").

Also remove code that sets alignment for ARM functions, which is redundant
with code in the MachineFunction constructor, and remove the hidden
-arm-align-constant-islands flag, which has been enabled by default since
r146739 (Dec 2011) and has probably received sufficient testing by now.

Differential Revision: http://reviews.llvm.org/D9138

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235636 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Fix compiler warnings in release build
Krzysztof Parzyszek [Thu, 23 Apr 2015 20:26:21 +0000 (20:26 +0000)]
[Hexagon] Fix compiler warnings in release build

Patch by Aditya Nandakumar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235635 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[getUnderlyingOjbects] Analyze loop PHIs further to remove false positives
Adam Nemet [Thu, 23 Apr 2015 20:09:20 +0000 (20:09 +0000)]
[getUnderlyingOjbects] Analyze loop PHIs further to remove false positives

Specifically, if a pointer accesses different underlying objects in each
iteration, don't look through the phi node defining the pointer.

The motivating case is the underlyling-objects-2.ll testcase.  Consider
the loop nest:

  int **A;
  for (i)
    for (j)
       A[i][j] = A[i-1][j] * B[j]

This loop is transformed by Load-PRE to stash away A[i] for the next
iteration of the outer loop:

  Curr = A[0];          // Prev_0
  for (i: 1..N) {
    Prev = Curr;        // Prev = PHI (Prev_0, Curr)
    Curr = A[i];
    for (j: 0..N)
       Curr[j] = Prev[j] * B[j]
  }

Since A[i] and A[i-1] are likely to be independent pointers,
getUnderlyingObjects should not assume that Curr and Prev share the same
underlying object in the inner loop.

If it did we would try to dependence-analyze Curr and Prev and the
analysis of the corresponding SCEVs would fail with non-constant
distance.

To fix this, the getUnderlyingObjects API is extended with an optional
LoopInfo parameter.  This is effectively what controls whether we want
the above behavior or the original.  Currently, I only changed to use
this approach for LoopAccessAnalysis.

The other testcase is to guard the opposite case where we do want to
look through the loop PHI.  If we step through an array by incrementing
a pointer, the underlying object is the incoming value of the phi as the
loop is entered.

Fixes rdar://problem/19566729

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235634 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[NVPTX] run SeparateConstOffsetFromGEP before SLSR
Jingyue Wu [Thu, 23 Apr 2015 20:00:04 +0000 (20:00 +0000)]
[NVPTX] run SeparateConstOffsetFromGEP before SLSR

Summary:
We pick this order because SeparateConstOffsetFromGEP may create more
opportunities for SLSR.

Test Plan:
reassociate-geps-and-slsr.ll
no performance regression on internal benchmarks

Reviewers: meheff

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D9230

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235632 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Add missing -mcpu=SI to assembler test
Tom Stellard [Thu, 23 Apr 2015 19:33:55 +0000 (19:33 +0000)]
R600/SI: Add missing -mcpu=SI to assembler test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235630 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Add assembler support for all CI and VI VOP1 instructions
Tom Stellard [Thu, 23 Apr 2015 19:33:54 +0000 (19:33 +0000)]
R600/SI: Add assembler support for all CI and VI VOP1 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235629 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: v_mov_fed_b32 does not exist on VI
Tom Stellard [Thu, 23 Apr 2015 19:33:52 +0000 (19:33 +0000)]
R600/SI: v_mov_fed_b32 does not exist on VI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235628 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Use a better error message for unsupported instructions in the assembler
Tom Stellard [Thu, 23 Apr 2015 19:33:51 +0000 (19:33 +0000)]
R600/SI: Use a better error message for unsupported instructions in the assembler

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235627 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Improve AsmParser support for forced e64 encoding
Tom Stellard [Thu, 23 Apr 2015 19:33:48 +0000 (19:33 +0000)]
R600/SI: Improve AsmParser support for forced e64 encoding

We can now force e64 encoding even when the operands would be legal
for e32 encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235626 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Handle stubs for outlined functions that have only unreached terminators.
Andrew Kaylor [Thu, 23 Apr 2015 18:37:39 +0000 (18:37 +0000)]
[WinEH] Handle stubs for outlined functions that have only unreached terminators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235618 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert "[SEH] Remove the old __C_specific_handler code now that WinEHPrepare works"
Reid Kleckner [Thu, 23 Apr 2015 18:34:01 +0000 (18:34 +0000)]
Revert "[SEH] Remove the old __C_specific_handler code now that WinEHPrepare works"

We still have some "uses remain after removal" issues in -O0 builds.

This reverts commit r235557.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235617 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Enable printing instructions using aliases
Hal Finkel [Thu, 23 Apr 2015 18:30:38 +0000 (18:30 +0000)]
[PowerPC] Enable printing instructions using aliases

TableGen had been nicely generating code to print a number of instructions using
shorter aliases (and PowerPC has plenty of short mnemonics), but we were not
calling it. For some of the aliases we support in the parser, TableGen can't
infer the "inverse" alias relationship, so there is still more to do.

Thus, after some hours of updating test cases...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove DIContext.h to common DebugInfo location.
Zachary Turner [Thu, 23 Apr 2015 17:37:47 +0000 (17:37 +0000)]
Move DIContext.h to common DebugInfo location.

This will enable us to create a PDBContext so as to expose some
amount of debug info functionality through a common interace.

Differential Revision: http://reviews.llvm.org/D9205
Reviewed by: Alexey Samsonov

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235612 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove Value.isDereferenceablePointer to ValueTracking [NFC]
Philip Reames [Thu, 23 Apr 2015 17:36:48 +0000 (17:36 +0000)]
Move Value.isDereferenceablePointer to ValueTracking [NFC]

Move isDereferenceablePointer function to Analysis. This function recursively tracks dereferencability over a chain of values like other functions in ValueTracking.

This refactoring is motivated by further changes to support dereferenceable_or_null attribute (http://reviews.llvm.org/D8650). isDereferenceablePointer will be extended to perform context-sensitive analysis and IR is not a good place to have such functionality.

Patch by: Artur Pilipenko <apilipenko@azulsystems.com>
Differential Revision: reviews.llvm.org/D9075

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235611 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AArch64] Add nvcast patterns for v4f16 and v8f16
Pirama Arumuga Nainar [Thu, 23 Apr 2015 17:32:25 +0000 (17:32 +0000)]
[AArch64] Add nvcast patterns for v4f16 and v8f16

Summary:
Constant stores of f16 vectors can create NvCast nodes from various
operand types to v4f16 or v8f16 depending on patterns in the stored
constants.  This patch adds nvcast rules with v4f16 and v8f16 values.

AArchISelLowering::LowerBUILD_VECTOR has the details on which constant
patterns generate the nvcast nodes.

Reviewers: jmolloy, srhines, ab

Subscribers: rengolin, aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D9201

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235610 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AArch64] Handle vec4, vec8, vec16 *itofp for half
Pirama Arumuga Nainar [Thu, 23 Apr 2015 17:16:27 +0000 (17:16 +0000)]
[AArch64] Handle vec4, vec8, vec16 *itofp for half

Summary:
Set operation action for SINT_TO_FP and UINT_TO_FP nodes with v4i32,
v8i8, v8i16 inputs to allow promotion of v4f16 results.

Add tests for sitofp and uitofp for vec4, vec8, vec16, and i8, i16, i32,
and i64 vectors.  Only missing tests are for v16i8 and v16i16 as the
shift operations are too complicated to write a proper check sequence.

The conversions from v4i64 to v4f16 do not depend on this patch - v4i64
is split and the conversion gets handled while lowering v2i64.  I am
adding a test here for completeness.

Reviewers: aemerson, rengolin, ab, jmolloy, srhines

Subscribers: rengolin, aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D9166

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235609 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRe-commit r235560: Switch lowering: extract jump tables and bit tests before building...
Hans Wennborg [Thu, 23 Apr 2015 16:45:24 +0000 (16:45 +0000)]
Re-commit r235560: Switch lowering: extract jump tables and bit tests before building binary tree (PR22262)

Third time's the charm. The previous commit was reverted as a
reverse for-loop in SelectionDAGBuilder::lowerWorkItem did 'I--'
on an iterator at the beginning of a vector, causing asserts
when using debugging iterators. This commit fixes that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235608 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agouse update_llc_test_checks.py to tighten checking; remove unnecessary CPU param
Sanjay Patel [Thu, 23 Apr 2015 16:07:50 +0000 (16:07 +0000)]
use update_llc_test_checks.py to tighten checking; remove unnecessary CPU param

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235604 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Shrink-wrap stack frame (Hexagon-specific)
Krzysztof Parzyszek [Thu, 23 Apr 2015 16:05:39 +0000 (16:05 +0000)]
[Hexagon] Shrink-wrap stack frame (Hexagon-specific)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235603 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Add testcases for stack alignment and variable-sized objects
Krzysztof Parzyszek [Thu, 23 Apr 2015 15:12:49 +0000 (15:12 +0000)]
[Hexagon] Add testcases for stack alignment and variable-sized objects

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235602 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] [IAS] Move NOP emission after pseudo-instruction expansion. NFC.
Toma Tabacu [Thu, 23 Apr 2015 14:48:38 +0000 (14:48 +0000)]
[mips] [IAS] Move NOP emission after pseudo-instruction expansion. NFC.

As suggested in the review for http://reviews.llvm.org/D8537.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235601 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert r235560; this commit was causing several failed assertions in Debug builds...
Aaron Ballman [Thu, 23 Apr 2015 13:41:59 +0000 (13:41 +0000)]
Revert r235560; this commit was causing several failed assertions in Debug builds using MSVC's STL. The iterator is being used outside of its valid range.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235597 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoBe more strict about the operand for the array type in BitcodeReader
Filipe Cabecinhas [Thu, 23 Apr 2015 13:38:21 +0000 (13:38 +0000)]
Be more strict about the operand for the array type in BitcodeReader

Summary: Bug found with AFL fuzz.

Reviewers: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235596 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoVerify sizes when trying to read a BitcodeAbbrevOp
Filipe Cabecinhas [Thu, 23 Apr 2015 13:25:35 +0000 (13:25 +0000)]
Verify sizes when trying to read a BitcodeAbbrevOp

Summary:
Make sure the abbrev operands are valid and that we can read/skip them
afterwards.

Bug found with AFL fuzz.

Reviewers: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9030

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235595 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[DAGCombiner] Remove extra bitcasts surrounding vector shuffles
Simon Pilgrim [Thu, 23 Apr 2015 08:43:13 +0000 (08:43 +0000)]
[DAGCombiner] Remove extra bitcasts surrounding vector shuffles

Patch to remove extra bitcasts from shuffles, this is often a legacy of XformToShuffleWithZero being used to combine bitmaskings (of float vectors bitcast to integer vectors) into shuffles: bitcast(shuffle(bitcast(s0),bitcast(s1))) -> shuffle(s0,s1)

Differential Revision: http://reviews.llvm.org/D9097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235578 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove common loop utility function isInductionPHI into LoopUtils.cpp
Karthik Bhat [Thu, 23 Apr 2015 08:29:20 +0000 (08:29 +0000)]
Move common loop utility function isInductionPHI into LoopUtils.cpp

This patch refactors the definition of common utility function "isInductionPHI" to LoopUtils.cpp.
This fixes compilation error when configured with -DBUILD_SHARED_LIBS=ON

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235577 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd support to interchange loops with reductions.
Karthik Bhat [Thu, 23 Apr 2015 04:51:44 +0000 (04:51 +0000)]
Add support to interchange loops with reductions.
This patch enables interchanging of tightly nested loops with reductions.
Differential Revision: http://reviews.llvm.org/D8314

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235571 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Removing seh-filter.ll until I can determine its validity
Andrew Kaylor [Thu, 23 Apr 2015 00:38:22 +0000 (00:38 +0000)]
[WinEH] Removing seh-filter.ll until I can determine its validity

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235566 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Don't skip landing pads that end with an unreachable instruction.
Andrew Kaylor [Thu, 23 Apr 2015 00:20:44 +0000 (00:20 +0000)]
[WinEH] Don't skip landing pads that end with an unreachable instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235563 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSwitch lowering: extract jump tables and bit tests before building binary tree (PR22262)
Hans Wennborg [Wed, 22 Apr 2015 23:14:56 +0000 (23:14 +0000)]
Switch lowering: extract jump tables and bit tests before building binary tree (PR22262)

This is a re-commit of r235101, which also fixes the problems with the previous patch:

- Switches with only a default case and non-fallthrough were handled incorrectly

- The previous patch tickled a bug in PowerPC Early-Return Creation which is fixed here.

> This is a major rewrite of the SelectionDAG switch lowering. The previous code
> would lower switches as a binary tre, discovering clusters of cases
> suitable for lowering by jump tables or bit tests as it went along. To increase
> the likelihood of finding jump tables, the binary tree pivot was selected to
> maximize case density on both sides of the pivot.
>
> By not selecting the pivot in the middle, the binary trees would not always
> be balanced, leading to performance problems in the generated code.
>
> This patch rewrites the lowering to search for clusters of cases
> suitable for jump tables or bit tests first, and then builds the binary
> tree around those clusters. This way, the binary tree will always be balanced.
>
> This has the added benefit of decoupling the different aspects of the lowering:
> tree building and jump table or bit tests finding are now easier to tweak
> separately.
>
> For example, this will enable us to balance the tree based on profile info
> in the future.
>
> The algorithm for finding jump tables is quadratic, whereas the previous algorithm
> was O(n log n) for common cases, and quadratic only in the worst-case. This
> doesn't seem to be major problem in practice, e.g. compiling a file consisting
> of a 10k-case switch was only 30% slower, and such large switches should be rare
> in practice. Compiling e.g. gcc.c showed no compile-time difference.  If this
> does turn out to be a problem, we could limit the search space of the algorithm.
>
> This commit also disables all optimizations during switch lowering in -O0.
>
> Differential Revision: http://reviews.llvm.org/D8649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235560 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[InstCombine] Use a more targeted fix instead of r235544
David Majnemer [Wed, 22 Apr 2015 22:42:05 +0000 (22:42 +0000)]
[InstCombine] Use a more targeted fix instead of r235544

Only clear out the NSW/NUW flags if we are optimizing 'add'/'sub' while
taking advantage that the sign bit is not set.  We do this optimization
to further shrink the mask but shrinking the mask isn't NSW/NUW
preserving in this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235558 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SEH] Remove the old __C_specific_handler code now that WinEHPrepare works
Reid Kleckner [Wed, 22 Apr 2015 22:13:09 +0000 (22:13 +0000)]
[SEH] Remove the old __C_specific_handler code now that WinEHPrepare works

This removes the -sehprepare flag and makes __C_specific_handler
functions always to use WinEHPrepare.

This was tested by building all of chromium_builder_tests and running a
few tests that use SEH, but if something breaks, we can revert this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235557 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUnxfail passing test on Hexagon
Krzysztof Parzyszek [Wed, 22 Apr 2015 21:41:24 +0000 (21:41 +0000)]
Unxfail passing test on Hexagon

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235556 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[RuntimeDyld][COFF] Add external symbol resolution support to RuntimeDyldCOFF.
Lang Hames [Wed, 22 Apr 2015 21:38:37 +0000 (21:38 +0000)]
[RuntimeDyld][COFF] Add external symbol resolution support to RuntimeDyldCOFF.

Patch by Andy Ayers. Thanks Andy!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235554 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Some cleanup of instruction selection code
Krzysztof Parzyszek [Wed, 22 Apr 2015 21:17:00 +0000 (21:17 +0000)]
[Hexagon] Some cleanup of instruction selection code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235552 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Demote values and phis live across exception handlers up front
Reid Kleckner [Wed, 22 Apr 2015 21:05:21 +0000 (21:05 +0000)]
[WinEH] Demote values and phis live across exception handlers up front

In particular, this handles SSA values that are live *out* of a handler.
The existing code only handles values that are live *in* to a handler.

It also handles phi nodes in the block where normal control should
resume after the end of a catch handler.  When EH return points have phi
nodes, we need to split the return edge. It is impossible for phi
elimination to emit copies in the previous block if that block gets
outlined. The indirectbr that we leave in the function is only notional,
and is eliminated from the MachineFunction CFG early on.

Reviewers: majnemer, andrew.w.kaylor

Differential Revision: http://reviews.llvm.org/D9158

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235545 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[InstCombine] Clear out nsw/nuw if we modify computation in the chain
David Majnemer [Wed, 22 Apr 2015 20:59:28 +0000 (20:59 +0000)]
[InstCombine] Clear out nsw/nuw if we modify computation in the chain

An nsw/nuw operation relies on the values feeding into it to not
overflow if 'poison' is not to be produced.  This means that
optimizations which make modifications to the bottom of a chain (like
SimplifyDemandedBits) must strip out nsw/nuw if they cannot ensure that
they will be preserved.

This fixes PR23309.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235544 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Kaleidoscope] Fix incorrect use of reinterpret_cast.
Lang Hames [Wed, 22 Apr 2015 20:58:34 +0000 (20:58 +0000)]
[Kaleidoscope] Fix incorrect use of reinterpret_cast.

Thanks to Dave Blaikie for catching this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235543 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Allocator] Remove memory poisoning before deallocation
Reid Kleckner [Wed, 22 Apr 2015 20:56:42 +0000 (20:56 +0000)]
[Allocator] Remove memory poisoning before deallocation

I added the poisoning back in r76891 (2009) because of some bugs in
Unladen Swallow, and then Evan Cheng added the setRangeWritable() call
in r81308. Profiling a Release+Asserts build on Windows shows that this
memory protection call is actually very expensive. 4 seconds of a 70
second Clang compilation are spent in VirtualQuery. These days we have
more reliable tools like ASan to find these kinds of bugs, so we can go
ahead and retire these checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235542 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Kaleidoscope] Remove RTTI use from chapters 7 and 8.
Lang Hames [Wed, 22 Apr 2015 20:41:34 +0000 (20:41 +0000)]
[Kaleidoscope] Remove RTTI use from chapters 7 and 8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235541 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAnother test to exercise APInt divide step D6.
Yaron Keren [Wed, 22 Apr 2015 18:49:59 +0000 (18:49 +0000)]
Another test to exercise APInt divide step D6.

This is divrem_big7 since divrem_big6 is used in Pawel upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235536 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Use A2_tfrsi for constant pool and jump table addresses
Krzysztof Parzyszek [Wed, 22 Apr 2015 18:25:53 +0000 (18:25 +0000)]
[Hexagon] Use A2_tfrsi for constant pool and jump table addresses

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235535 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert "[opaque pointer type] Avoid using PointerType::getElementType for a few cases...
David Blaikie [Wed, 22 Apr 2015 18:16:49 +0000 (18:16 +0000)]
Revert "[opaque pointer type] Avoid using PointerType::getElementType for a few cases of CallInst"

This reverts commit r235458.

It looks like this might be breaking something LTO-ish. Looking into it
& will recommit with a fix/test case/etc once I've got more to go on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235533 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AArch64] Use MachineRegisterInfo instead of LiveIntervals to calculate liveness...
Pete Cooper [Wed, 22 Apr 2015 18:05:13 +0000 (18:05 +0000)]
[AArch64] Use MachineRegisterInfo instead of LiveIntervals to calculate liveness.  NFC.

The CondOpt pass currently uses LiveIntervals to set the dead flag on a def.  This patch uses MachineRegisterInfo::use_empty instead as that is equivalent to the def being dead.

This removes an instance of LiveIntervals in the pass manager pipeline and saves 3.8% of compile time on llc conpiled for AArch64.

Reviewed by Chad Rosier and Zhaoshi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235532 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agodon't repeat function names in comments; NFC
Sanjay Patel [Wed, 22 Apr 2015 18:04:46 +0000 (18:04 +0000)]
don't repeat function names in comments; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235531 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix correctness check for test_vec_fpextend_double
Pirama Arumuga Nainar [Wed, 22 Apr 2015 18:04:12 +0000 (18:04 +0000)]
Fix correctness check for test_vec_fpextend_double

Summary:
Remove the CHECK-DAG calls introduced in r235341, and add a comment that
this test may break due to scheduling variations.

This patch completes the fix discussed in http://reviews.llvm.org/D8804

Reviewers: dsanders, srhines

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9178

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235530 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Consider constant-extended offsets to be valid
Krzysztof Parzyszek [Wed, 22 Apr 2015 17:51:26 +0000 (17:51 +0000)]
[Hexagon] Consider constant-extended offsets to be valid

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235529 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoChange MachineOperand::OpKind from unsigned char to a bitfield. NFC.
Pete Cooper [Wed, 22 Apr 2015 17:48:26 +0000 (17:48 +0000)]
Change MachineOperand::OpKind from unsigned char to a bitfield.  NFC.

This causes OpKind and all the bitfields after it to use 32-bit load/stores instead of i24's for the existing bitfields.

Bugs will be filed to track whether clang and llvm could have generated the 32-bit operations in the front-end or optimizer.

Reviewed by Rafael.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235528 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTest commit: fix typo in comment.
Luqman Aden [Wed, 22 Apr 2015 17:42:37 +0000 (17:42 +0000)]
Test commit: fix typo in comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235526 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix Windows build break: use LLVM_FUNCTION_NAME instead of __func__.
Krzysztof Parzyszek [Wed, 22 Apr 2015 17:19:44 +0000 (17:19 +0000)]
Fix Windows build break: use LLVM_FUNCTION_NAME instead of __func__.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235525 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600: Fix always inline pass breaking noinline functions
Matt Arsenault [Wed, 22 Apr 2015 17:10:44 +0000 (17:10 +0000)]
R600: Fix always inline pass breaking noinline functions

No test since calls are not actually supported yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235524 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRecommit r235219, it's need for out-of-tree users of AlignOf.h.
Yaron Keren [Wed, 22 Apr 2015 16:43:56 +0000 (16:43 +0000)]
Recommit r235219, it's need for out-of-tree users of AlignOf.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235522 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Overhaul of stack object allocation
Krzysztof Parzyszek [Wed, 22 Apr 2015 16:43:53 +0000 (16:43 +0000)]
[Hexagon] Overhaul of stack object allocation

- Use static allocation for aligned stack objects.
- Simplify dynamic stack object allocation.
- Simplify elimination of frame-indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235521 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[opaque pointer type] Use pointee type retrieved from asm, rather than accessing...
David Blaikie [Wed, 22 Apr 2015 16:37:35 +0000 (16:37 +0000)]
[opaque pointer type] Use pointee type retrieved from asm, rather than accessing it via the pointer type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235520 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[cmake] Quote the path to the target exports file, fixes PR23313
Reid Kleckner [Wed, 22 Apr 2015 16:23:00 +0000 (16:23 +0000)]
[cmake] Quote the path to the target exports file, fixes PR23313

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235519 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] Add store-folded memop patterns for vcvtps2ph
Sanjay Patel [Wed, 22 Apr 2015 16:11:19 +0000 (16:11 +0000)]
[x86] Add store-folded memop patterns for vcvtps2ph

Differential Revision: http://reviews.llvm.org/D7296

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235517 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Treat CFI as solo instructions
Krzysztof Parzyszek [Wed, 22 Apr 2015 15:47:35 +0000 (15:47 +0000)]
[Hexagon] Treat CFI as solo instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235516 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Implement HexagonInstPrinter::printRegName
Krzysztof Parzyszek [Wed, 22 Apr 2015 15:38:17 +0000 (15:38 +0000)]
[Hexagon] Implement HexagonInstPrinter::printRegName

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235514 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSupport arm32 R_ARM_V4BX relocation format
Adhemerval Zanella [Wed, 22 Apr 2015 15:26:43 +0000 (15:26 +0000)]
Support arm32 R_ARM_V4BX relocation format

ARM32 ELF R_ARM_V4BX relocation format is a special relocation type
that records the location of an ARMv4t BX instruction to enable a
static linker to generate ARMv4 compatible instructions.  This
relocation does not contain a reference symbol.

This patch enabled its creation by removing the requeriment of a
relocation symbol target in ELFState<ELFT>::writeSectionContent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235513 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix a type mismatch assert in SCEV division
Brendon Cahoon [Wed, 22 Apr 2015 15:06:40 +0000 (15:06 +0000)]
Fix a type mismatch assert in SCEV division

An assert was triggered when attempting to create a new SCEV
with operands of different types in the visitAddRecExpr. In this
test case, the operand types of the numerator and denominator
are different. The SCEV division code should generate a
conservative answer when this happens.

Differential Revision: http://reviews.llvm.org/D9021

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235511 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][AVX] Fix failure due to a missing ISel pattern to select VBROADCAST nodes ...
Andrea Di Biagio [Wed, 22 Apr 2015 14:53:39 +0000 (14:53 +0000)]
[X86][AVX] Fix failure due to a missing ISel pattern to select VBROADCAST nodes (PR23259).

This fixes a regression introduced at revision 218263.

On AVX, if we optimize for size, a splat build_vector of a load
is lowered into a VBROADCAST node. This is done even if the value type of the
splat build_vector node is v2i64.

Since AVX doesn't support v2f64/v2i64 broadcasts, revision 218263 added two
extra tablegen patterns to allow selecting a VMOVDDUPrm from an X86VBroadcast
where the scalar element comes from a loadi64/loadf64.

However, revision 218263 forgot to add an extra fallback pattern for the case
where we have a X86VBroadcast of a loadi64 with multiple uses.

This patch adds the missing tablegen pattern in X86InstrSSE.td.
This patch also adds an extra test to 'splat-for-size.ll' to verify that ISel
doesn't crash with a 'fatal error in the backend' due to a missing AVX pattern
to select v2i64 X86ISD::BROADCAST nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235509 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFixed logic to enable complex FMA formation.
Olivier Sallenave [Wed, 22 Apr 2015 14:07:26 +0000 (14:07 +0000)]
Fixed logic to enable complex FMA formation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235508 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips][microMIPSr6] Implement mips32 to microMIPSr6 mapping support
Zoran Jovanovic [Wed, 22 Apr 2015 13:27:34 +0000 (13:27 +0000)]
[mips][microMIPSr6] Implement mips32 to microMIPSr6 mapping support
Differential Revision: http://reviews.llvm.org/D8661

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235505 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[DAGCombine] Disable select(c, load,load) for indexed loads
Hal Finkel [Wed, 22 Apr 2015 11:32:25 +0000 (11:32 +0000)]
[DAGCombine] Disable select(c, load,load) for indexed loads

This turned up after r235333, but was a pre-existing bug. The optimization
which transforms select(c, load, load) into a load of a select of the addresses
does not handle indexed loads (pre/post inc/dec). However, it did not check for
them either, leading to a crash if it tried to transform one of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235497 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert "[mips][FastISel] Implement shift ops for Mips fast-isel."
Vasileios Kalintiris [Wed, 22 Apr 2015 10:08:46 +0000 (10:08 +0000)]
Revert "[mips][FastISel] Implement shift ops for Mips fast-isel."

This reverts commit r235194. It was causing a failure in FastISel buildbots
due to sign-extension issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235495 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AArch64] Disable complex GEP optimization by default.
James Molloy [Wed, 22 Apr 2015 09:11:38 +0000 (09:11 +0000)]
[AArch64] Disable complex GEP optimization by default.

Enough concerns were raised that this optimization is pessimising some code patterns.

The obvious fix, to add a Reassociate run afterwards, causes even more pessimisation in some cases due to fewer complex addressing modes being matched. As there isn't a trivial fix for this, backing this out by default until someone gets a chance to fix the addressing mode matcher.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235491 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoHave more strict type checks when creating BinOp nodes in BitcodeReader
Filipe Cabecinhas [Wed, 22 Apr 2015 09:06:21 +0000 (09:06 +0000)]
Have more strict type checks when creating BinOp nodes in BitcodeReader

Summary: Bug found with AFL.

Reviewers: rafael, bkramer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9015

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235489 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[patchpoint] Add support for symbolic patchpoint targets to SelectionDAG and the
Lang Hames [Wed, 22 Apr 2015 06:02:31 +0000 (06:02 +0000)]
[patchpoint] Add support for symbolic patchpoint targets to SelectionDAG and the
X86 backend.

The code generated for symbolic targets is identical to the code generated for
constant targets, except that a relocation is emitted to fix up the actual
target address at link-time. This allows IR and object files containing
patchpoints to be cached across JIT-invocations where the target address may
change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235483 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[TableGen] Use range based for loops.
Craig Topper [Wed, 22 Apr 2015 05:27:47 +0000 (05:27 +0000)]
[TableGen] Use range based for loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235482 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[TableGen] Remove some deletes that violate ownership semantics. These don't seem...
Craig Topper [Wed, 22 Apr 2015 05:27:11 +0000 (05:27 +0000)]
[TableGen] Remove some deletes that violate ownership semantics. These don't seem to execute in our codebase today and date back to a time when there was an allocation in this function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235481 91177308-0d34-0410-b5e6-96231b3b80d8