oota-llvm.git
9 years agoFixed unused variable warning.
Simon Pilgrim [Tue, 3 Feb 2015 20:38:52 +0000 (20:38 +0000)]
Fixed unused variable warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228025 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAllow PRE to insert no-cost phi nodes
Daniel Berlin [Tue, 3 Feb 2015 20:37:08 +0000 (20:37 +0000)]
Allow PRE to insert no-cost phi nodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228024 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][SSE] Added general integer shuffle matching for MOVQ instruction
Simon Pilgrim [Tue, 3 Feb 2015 20:09:18 +0000 (20:09 +0000)]
[X86][SSE] Added general integer shuffle matching for MOVQ instruction

This patch adds general shuffle pattern matching for the MOVQ zero-extend instruction (copy lower 64bits, zero upper) for all 128-bit integer vectors, it is added as a fallback test in lowerVectorShuffleAsZeroOrAnyExtend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228022 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Updating XTYPE/PRED intrinsics.
Colin LeMahieu [Tue, 3 Feb 2015 19:43:59 +0000 (19:43 +0000)]
[Hexagon] Updating XTYPE/PRED intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228019 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[fuzzer] update the include line to use the new header name
Kostya Serebryany [Tue, 3 Feb 2015 19:42:05 +0000 (19:42 +0000)]
[fuzzer] update the include line to use the new header name

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228018 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd straight-line strength reduction to LLVM
Jingyue Wu [Tue, 3 Feb 2015 19:37:06 +0000 (19:37 +0000)]
Add straight-line strength reduction to LLVM

Summary:
Straight-line strength reduction (SLSR) is implemented in GCC but not yet in
LLVM. It has proven to effectively simplify statements derived from an unrolled
loop, and can potentially benefit many other cases too. For example,

LLVM unrolls

  #pragma unroll
  foo (int i = 0; i < 3; ++i) {
    sum += foo((b + i) * s);
  }

into

  sum += foo(b * s);
  sum += foo((b + 1) * s);
  sum += foo((b + 2) * s);

However, no optimizations yet reduce the internal redundancy of the three
expressions:

  b * s
  (b + 1) * s
  (b + 2) * s

With SLSR, LLVM can optimize these three expressions into:

  t1 = b * s
  t2 = t1 + s
  t3 = t2 + s

This commit is only an initial step towards implementing a series of such
optimizations. I will implement more (see TODO in the file commentary) in the
near future. This optimization is enabled for the NVPTX backend for now.
However, I am more than happy to push it to the standard optimization pipeline
after more thorough performance tests.

Test Plan: test/StraightLineStrengthReduce/slsr.ll

Reviewers: eliben, HaoLiu, meheff, hfinkel, jholewinski, atrick

Reviewed By: jholewinski, atrick

Subscribers: karthikthecool, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D7310

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228016 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Updating XTYPE/PERM intrinsics.
Colin LeMahieu [Tue, 3 Feb 2015 19:36:59 +0000 (19:36 +0000)]
[Hexagon] Updating XTYPE/PERM intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228015 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][AVX2] Enabled shuffle matching for the AVX2 zero extension (128bit -> 256bit...
Simon Pilgrim [Tue, 3 Feb 2015 19:34:09 +0000 (19:34 +0000)]
[X86][AVX2] Enabled shuffle matching for the AVX2 zero extension (128bit -> 256bit) vpmovzx* instructions.

Differential Revision: http://reviews.llvm.org/D7251

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228014 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix duplicated symbol error.
Rafael Espindola [Tue, 3 Feb 2015 19:25:53 +0000 (19:25 +0000)]
Fix duplicated symbol error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228012 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix typo in test/CodeGen/X86/sibcall.ll (pr22331).
Rafael Espindola [Tue, 3 Feb 2015 19:20:26 +0000 (19:20 +0000)]
Fix typo in test/CodeGen/X86/sibcall.ll (pr22331).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228011 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding missing vector multiply instruction encodings. Converting multiply...
Colin LeMahieu [Tue, 3 Feb 2015 19:15:11 +0000 (19:15 +0000)]
[Hexagon] Adding missing vector multiply instruction encodings.  Converting multiply intrinsics and updating tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228010 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerge consecutive 16-byte loads into one 32-byte load (PR22329)
Sanjay Patel [Tue, 3 Feb 2015 18:54:00 +0000 (18:54 +0000)]
Merge consecutive 16-byte loads into one 32-byte load (PR22329)

This patch detects consecutive vector loads using the existing
EltsFromConsecutiveLoads() logic. This fixes:
http://llvm.org/bugs/show_bug.cgi?id=22329

This patch effectively reverts the tablegen additions of D6492 /
http://reviews.llvm.org/rL224344 ...which in hindsight were a horrible hack.

The test cases that were added with that patch are simply modified to load
from varying offsets of a base pointer. These loads did not match the existing
tablegen patterns.

A happy side effect of doing this optimization earlier is that we can now fold
the load into a math op where possible; this is shown in some of the updated
checks in the test file.

Differential Revision: http://reviews.llvm.org/D7303

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228006 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoremove variable names from comments; NFC
Sanjay Patel [Tue, 3 Feb 2015 18:47:32 +0000 (18:47 +0000)]
remove variable names from comments; NFC

I didn't bother to fix the self-referential definitions and grammar
because my eyes started to bleed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228004 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LTO API] split lto_codegen_compile to lto_codegen_optimize and
Manman Ren [Tue, 3 Feb 2015 18:39:15 +0000 (18:39 +0000)]
[LTO API] split lto_codegen_compile to lto_codegen_optimize and
lto_codegen_compile_optimized. Also add lto_api_version.

Before this commit, we can only dump the optimized bitcode after running
lto_codegen_compile, but it includes some impacts of running codegen passes,
one example is StackProtector pass. We will get assertion failure when running
llc on the optimized bitcode, because StackProtector is effectively run twice.

After splitting lto_codegen_compile, the linker can choose to dump the bitcode
before running lto_codegen_compile_optimized.

lto_api_version is added so ld64 can check for runtime-availability of the new
API.

rdar://19565500

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228000 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix ProgramFiles path for 64-bit Windows installer
Hans Wennborg [Tue, 3 Feb 2015 18:31:29 +0000 (18:31 +0000)]
Fix ProgramFiles path for 64-bit Windows installer

If we are building an 64bit installer on Windows we have to adjust the
Program Files path otherwise it uses the wrong Program Files (x86)
directory. Related CMake bug report
http://public.kitware.com/Bug/view.php?id=14211

Patch by Ismail Dönmez!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227999 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Converting complex number intrinsics and adding tests.
Colin LeMahieu [Tue, 3 Feb 2015 18:16:28 +0000 (18:16 +0000)]
[Hexagon] Converting complex number intrinsics and adding tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227995 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu.
Colin LeMahieu [Tue, 3 Feb 2015 18:01:45 +0000 (18:01 +0000)]
[Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227993 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LoopVectorize] Fix rebase glitch in r227751
Adam Nemet [Tue, 3 Feb 2015 17:59:53 +0000 (17:59 +0000)]
[LoopVectorize] Fix rebase glitch in r227751

LoopVectorizationLegality::{getNumLoads,getNumStores} should forward to
LoopAccessAnalysis now.

Thanks to Takumi for noticing this!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227992 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove usernames from TODOs, NFC
Jingyue Wu [Tue, 3 Feb 2015 17:57:38 +0000 (17:57 +0000)]
Remove usernames from TODOs, NFC

making the style consistent with the rest

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227991 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI
Marek Olsak [Tue, 3 Feb 2015 17:38:12 +0000 (17:38 +0000)]
R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI

This can happen when a REV instruction is commuted.

The trick is not to define the _vi versions of instructions, which has these
consequences:
- code generation will always fail if a pseudo cannot be lowered
  (very useful to catch bugs where an unsupported instruction somehow makes
   it to the printer)
- ability to query if a pseudo can be lowered, which is done in commuteOpcode
  to prevent REV from commuting to non-REV on VI

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227990 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Remove VOP2_REV definitions from target-specific instructions
Marek Olsak [Tue, 3 Feb 2015 17:38:05 +0000 (17:38 +0000)]
R600/SI: Remove VOP2_REV definitions from target-specific instructions

The getCommute* functions are only used with pseudos, so this commit doesn't
change anything.

The issue with missing non-rev versions of shift instructions on VI will fixed
separately.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227989 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Trivial instruction definition corrections for VI (v2)
Marek Olsak [Tue, 3 Feb 2015 17:38:01 +0000 (17:38 +0000)]
R600/SI: Trivial instruction definition corrections for VI (v2)

- V_MAC_LEGACY_F32 exists on VI, but it's VOP3-only.

- Define CVT_PK opcodes which are different between SI and VI. These are
  unused. The idea is to define all chip differences.

v2: keep V_MUL_LO_U32

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227988 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2
Marek Olsak [Tue, 3 Feb 2015 17:37:57 +0000 (17:37 +0000)]
R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2

These are VOP2 on SI and VOP3 on VI, and their pseudos are neither, which can
be a problem. In order to make isVOP2 and isVOP3 queries behave as expected,
the encoding must be determined first.

This doesn't fix any known issue, but better safe than sorry.

v2: add and use getMCOpcodeFromPseudo

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227987 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Fix dependency between instruction writing M0 and S_SENDMSG on VI (v2)
Marek Olsak [Tue, 3 Feb 2015 17:37:52 +0000 (17:37 +0000)]
R600/SI: Fix dependency between instruction writing M0 and S_SENDMSG on VI (v2)

This fixes a hang when using an empty geometry shader.

v2: - don't add s_nop when followed by s_waitcnt
    - comestic changes

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227986 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix program crashes due to alignment exceptions generated for SSE memop instructions...
Sanjay Patel [Tue, 3 Feb 2015 17:13:04 +0000 (17:13 +0000)]
Fix program crashes due to alignment exceptions generated for SSE memop instructions (PR22371).

r224330 introduced a bug by misinterpreting the "FeatureVectorUAMem" bit.
The commit log says that change did not affect anything, but that's not correct.
That change allowed SSE instructions to have unaligned mem operands folded into
math ops, and that's not allowed in the default specification for any SSE variant.

The bug is exposed when compiling for an AVX-capable CPU that had this feature
flag but without enabling AVX codegen. Another mistake in r224330 was not adding
the feature flag to all AVX CPUs; the AMD chips were excluded.

This is part of the fix for PR22371 ( http://llvm.org/bugs/show_bug.cgi?id=22371 ).

This feature bit is SSE-specific, so I've renamed it to "FeatureSSEUnalignedMem".
Changed the existing test case for the feature bit to reflect the new name and
renamed the test file itself to better reflect the feature.
Added runs to fold-vex.ll to check for the failing codegen.

Note that the feature bit is not set by default on any CPU because it may require a
configuration register setting to enable the enhanced unaligned behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227983 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDisable 32-bit tests in tls-pic.ll until they can be repaired
Bill Schmidt [Tue, 3 Feb 2015 16:57:38 +0000 (16:57 +0000)]
Disable 32-bit tests in tls-pic.ll until they can be repaired

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227981 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFurther revise too-restrictive test CodeGen/PowerPC/tls-pic.ll
Bill Schmidt [Tue, 3 Feb 2015 16:33:55 +0000 (16:33 +0000)]
Further revise too-restrictive test CodeGen/PowerPC/tls-pic.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227980 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFurther revise too-restrictive test CodeGen/PowerPC/tls-pic.ll
Bill Schmidt [Tue, 3 Feb 2015 16:29:52 +0000 (16:29 +0000)]
Further revise too-restrictive test CodeGen/PowerPC/tls-pic.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227978 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevise too-restrictive test CodeGen/PowerPC/tls-pic.ll
Bill Schmidt [Tue, 3 Feb 2015 16:24:05 +0000 (16:24 +0000)]
Revise too-restrictive test CodeGen/PowerPC/tls-pic.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227977 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Yet another approach to __tls_get_addr
Bill Schmidt [Tue, 3 Feb 2015 16:16:01 +0000 (16:16 +0000)]
[PowerPC] Yet another approach to __tls_get_addr

This patch is a third attempt to properly handle the local-dynamic and
global-dynamic TLS models.

In my original implementation, calls to __tls_get_addr were hidden
from view until the asm-printer phase, at which point the underlying
branch-and-link instruction was created with proper relocations.  This
mostly worked well, but I used some repellent techniques to ensure
that the TLS_GET_ADDR nodes at the SD and MI levels correctly received
input from GPR3 and produced output into GPR3.  This proved to work
badly in the presence of multiple TLS variable accesses, with the
copies to and from GPR3 being scheduled incorrectly and generally
creating havoc.

In r221703, I addressed that problem by representing the calls to
__tls_get_addr as true calls during instruction lowering.  This had
the advantage of removing all of the bad hacks and relying on the
existing call machinery to properly glue the copies in place. It
looked like this was going to be the right way to go.

However, as a side effect of the recent discovery of problems with
linker optimizations for TLS, we discovered cases of suboptimal code
generation with this strategy.  The problem comes when tls_get_addr is
called for the same address, and there is a resulting CSE
opportunity.  It turns out that in such cases MachineCSE will common
the addis/addi instructions that set up the input value to
tls_get_addr, but will not common the calls themselves.  MachineCSE
does not have any machinery to common idempotent calls.  This is
perfectly sensible, since presumably this would be done at the IR
level, and introducing calls in the back end isn't commonplace.  In
any case, we end up with two calls to __tls_get_addr when one would
suffice, and that isn't good.

I presumed that the original design would have allowed commoning of
the machine-specific nodes that hid the __tls_get_addr calls, so as
suggested by Ulrich Weigand, I went back to that design and cleaned it
up so that the copies were properly held together by glue
nodes.  However, it turned out that this didn't work either...the
presence of copies to physical registers kept the machine-specific
nodes from being commoned also.

All of which leads to the design presented here.  This is a return to
the original design, except that no attempt is made to introduce
copies to and from GPR3 during instruction lowering.  Virtual registers
are used until prior to register allocation.  At that point, a special
pass is run that identifies the machine-specific nodes that hide the
tls_get_addr calls and introduces the copies to and from GPR3 around
them.  The register allocator then coalesces these copies away.  With
this design, MachineCSE succeeds in commoning tls_get_addr calls where
possible, and we get nice optimal code generation (better than GCC at
the moment, which does not common these calls).

One additional problem must be dealt with:  After introducing the
mentions of the physical register GPR3, the aggressive anti-dependence
breaker sees opportunities to improve scheduling by selecting a
different register instead.  Flags must be used on the instruction
descriptions to tell the anti-dependence breaker to keep its hands in
its pockets.

One thing missing from the original design was recording a definition
of the link register on the GET_TLS_ADDR nodes.  Doing this was found
to be insufficient to force a stack frame to be created, which led to
looping behavior because two different LR values were stored at the
same address.  This appears to have been an oversight in
PPCFrameLowering::determineFrameLayout(), which is repaired here.

Because MustSaveLR() returns true for calls to builtin_return_address,
this changed the expected behavior of
test/CodeGen/PowerPC/retaddr2.ll, which now stacks a frame but
formerly did not.  I've fixed the test case to reflect this.

There are existing TLS tests to catch regressions; the checks in
test/CodeGen/PowerPC/tls-store2.ll proved to be too restrictive in the
face of instruction scheduling with these changes, so I fixed that
up.

I've added a new test case based on the PrettyStackTrace module that
demonstrated the original problem. This checks that we get correct
code generation and that CSE of the calls to __get_tls_addr has taken
place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227976 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoImprove test to actually check for a folded load.
Sanjay Patel [Tue, 3 Feb 2015 15:37:18 +0000 (15:37 +0000)]
Improve test to actually check for a folded load.

This test was checking for lack of a "movaps" (an aligned load)
rather than a "movups" (an unaligned load). It also included
a store which complicated the checking.

Add specific CPU runs to prevent subtarget feature flag overrides
from inhibiting this optimization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227972 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][MMX] Improve transfer from mmx to i32
Bruno Cardoso Lopes [Tue, 3 Feb 2015 14:46:49 +0000 (14:46 +0000)]
[X86][MMX] Improve transfer from mmx to i32

Improve EXTRACT_VECTOR_ELT DAG combine to catch conversion patterns
between x86mmx and i32 with more layers of indirection.

Before:
  movq2dq %mm0, %xmm0
  movd %xmm0, %eax
After:
  movd %mm0, %eax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227969 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdding AArch64 support to ASan instrumentation
Renato Golin [Tue, 3 Feb 2015 11:20:45 +0000 (11:20 +0000)]
Adding AArch64 support to ASan instrumentation

For the time being, it is still hardcoded to support only the 39 VA bits
variant, I plan to work on supporting 42 and 48 VA bits variants, but I
don't have access to such hardware at the moment.

Patch by Chrystophe Lyon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227965 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax...
Craig Topper [Tue, 3 Feb 2015 11:03:57 +0000 (11:03 +0000)]
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227963 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Add Requires[In64BitMode] around MOVSX64rr32/MOVSX64rm32. This makes it more...
Craig Topper [Tue, 3 Feb 2015 11:03:43 +0000 (11:03 +0000)]
[X86] Add Requires[In64BitMode] around MOVSX64rr32/MOVSX64rm32. This makes it more strictly mutexed with the ARPL instruction 32-bit mode. Helps with some disassembler changes I'm experimenting with. Should be NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227962 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoOnly access TLOF via the TargetMachine, not TargetLowering.
Eric Christopher [Tue, 3 Feb 2015 07:22:52 +0000 (07:22 +0000)]
Only access TLOF via the TargetMachine, not TargetLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227949 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDefine a runOnMachineFunction for the Hexagon AsmPrinter and
Eric Christopher [Tue, 3 Feb 2015 06:40:22 +0000 (06:40 +0000)]
Define a runOnMachineFunction for the Hexagon AsmPrinter and
use it to initialize the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227948 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMigrate away from using a Subtarget except for the one place we want
Eric Christopher [Tue, 3 Feb 2015 06:40:19 +0000 (06:40 +0000)]
Migrate away from using a Subtarget except for the one place we want
to use it. Use the triple to determine OS format bits at the module
level.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227947 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PBQP Regalloc] Pre-spill vregs that have no legal physregs.
Lang Hames [Tue, 3 Feb 2015 06:14:06 +0000 (06:14 +0000)]
[PBQP Regalloc] Pre-spill vregs that have no legal physregs.

The PBQP::RegAlloc::MatrixMetadata class assumes that matrices have at least two
rows/columns (for the spill option plus at least one physreg). This patch
ensures that that invariant is met by pre-spilling vregs that have no physreg
options so that no node (and no corresponding edges) need be added to the PBQP
graph.

This fixes a bug in an out-of-tree target that was identified by Jonas Paulsson.
Thanks for tracking this down Jonas!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227942 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoResurrect initializers for NumLoads and NumStores in LoopVectorizationLegality to...
NAKAMURA Takumi [Tue, 3 Feb 2015 03:55:06 +0000 (03:55 +0000)]
Resurrect initializers for NumLoads and NumStores in LoopVectorizationLegality to suppress undefined behavior.

FIXME: Shall they be managed in LAA?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227940 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReally, really, really don't build llvm-pdbdump on MSVC < 2013.
Andrew Kaylor [Tue, 3 Feb 2015 03:08:25 +0000 (03:08 +0000)]
Really, really, really don't build llvm-pdbdump on MSVC < 2013.

There was a typo in the last attempt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227937 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPropagate a better error message to the C api.
Rafael Espindola [Tue, 3 Feb 2015 01:53:03 +0000 (01:53 +0000)]
Propagate a better error message to the C api.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227934 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse a non-fatal diag handler in the C API. FIxes PR22368.
Rafael Espindola [Tue, 3 Feb 2015 00:49:57 +0000 (00:49 +0000)]
Use a non-fatal diag handler in the C API. FIxes PR22368.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227903 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstrProf: Simplify RawCoverageMappingReader's API slightly
Justin Bogner [Tue, 3 Feb 2015 00:20:11 +0000 (00:20 +0000)]
InstrProf: Simplify RawCoverageMappingReader's API slightly

This is still kind of a weird API, but dropping the (partial) update
of the passed in CoverageMappingRecord makes it a little easier to
understand and use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227900 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstrProf: Simplify some logic by using ArrayRef::slice (NFC)
Justin Bogner [Tue, 3 Feb 2015 00:00:00 +0000 (00:00 +0000)]
InstrProf: Simplify some logic by using ArrayRef::slice (NFC)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227898 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert part of r227437 as it was unnecessary. Thanks to echristo for
Alex Rosenberg [Mon, 2 Feb 2015 23:58:54 +0000 (23:58 +0000)]
Revert part of r227437 as it was unnecessary. Thanks to echristo for
pointing this out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227897 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMigrate to using the subtarget on the machine function and update
Eric Christopher [Mon, 2 Feb 2015 23:03:45 +0000 (23:03 +0000)]
Migrate to using the subtarget on the machine function and update
all uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227891 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse the function template getSubtarget off of the machine function,
Eric Christopher [Mon, 2 Feb 2015 23:03:43 +0000 (23:03 +0000)]
Use the function template getSubtarget off of the machine function,
and use it in all locations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227890 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse the cached subtarget on the MachineFunction.
Eric Christopher [Mon, 2 Feb 2015 22:40:56 +0000 (22:40 +0000)]
Use the cached subtarget on the MachineFunction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227885 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove dead header.
Eric Christopher [Mon, 2 Feb 2015 22:40:54 +0000 (22:40 +0000)]
Remove dead header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227884 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove dead code in the HexagonMCInst classes. This also fixes
Eric Christopher [Mon, 2 Feb 2015 22:40:53 +0000 (22:40 +0000)]
Remove dead code in the HexagonMCInst classes. This also fixes
a layering violation in the port and removes calls to getSubtargetImpl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227883 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago80-col fixup.
Eric Christopher [Mon, 2 Feb 2015 22:40:51 +0000 (22:40 +0000)]
80-col fixup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227882 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInstrProf: Remove an unused header (NFC)
Justin Bogner [Mon, 2 Feb 2015 22:38:39 +0000 (22:38 +0000)]
InstrProf: Remove an unused header (NFC)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227881 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove dead code in the HexagonMCInst classes. This also fixes
Eric Christopher [Mon, 2 Feb 2015 22:28:48 +0000 (22:28 +0000)]
Remove dead code in the HexagonMCInst classes. This also fixes
a layering violation in the port and removes calls to getSubtargetImpl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227880 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago80-col fixup.
Eric Christopher [Mon, 2 Feb 2015 22:28:46 +0000 (22:28 +0000)]
80-col fixup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227879 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove unused class variables and update all callers/uses from
Eric Christopher [Mon, 2 Feb 2015 22:28:44 +0000 (22:28 +0000)]
Remove unused class variables and update all callers/uses from
the HexagonSplitTFRCondSet pass. Use the subtarget off the machine
function at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227878 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMigrate the HexagonSplitConst32AndConst64 pass from TargetMachine
Eric Christopher [Mon, 2 Feb 2015 22:11:43 +0000 (22:11 +0000)]
Migrate the HexagonSplitConst32AndConst64 pass from TargetMachine
based getSubtarget to the one cached on the MachineFunction.
Remove unused class variables and update all callers/uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227874 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove #if'd code and update comment.
Eric Christopher [Mon, 2 Feb 2015 22:11:42 +0000 (22:11 +0000)]
Remove #if'd code and update comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227873 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove HexagonMachineScheduler to use the subtarget off of the
Eric Christopher [Mon, 2 Feb 2015 22:11:40 +0000 (22:11 +0000)]
Move HexagonMachineScheduler to use the subtarget off of the
MachineFunction and update all uses accordingly including
VLIWResourceModel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227872 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoCache and use the subtarget that owns the target lowering.
Eric Christopher [Mon, 2 Feb 2015 22:11:36 +0000 (22:11 +0000)]
Cache and use the subtarget that owns the target lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227871 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][MMX] Add tests for MMX extract element
Bruno Cardoso Lopes [Mon, 2 Feb 2015 22:00:48 +0000 (22:00 +0000)]
[X86][MMX] Add tests for MMX extract element

LLVM ToT produces poor MMX code compared to 3.5. However, part of the previous
functionality can be achieved by using -x86-experimental-vector-widening-legalization.
Add tests to be sure we don't regress again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227869 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][MMX] Cleanup shuffle, bitcast and insert element tests
Bruno Cardoso Lopes [Mon, 2 Feb 2015 21:56:11 +0000 (21:56 +0000)]
[X86][MMX] Cleanup shuffle, bitcast and insert element tests

- Merge MMX arg passing test files
- Merge MMX bitcast, insert elt and shuffle tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227867 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agobpf: Use the getSubtarget call off of the MachineFunction rather than the TargetMachine
Alexei Starovoitov [Mon, 2 Feb 2015 21:24:27 +0000 (21:24 +0000)]
bpf: Use the getSubtarget call off of the MachineFunction rather than the TargetMachine

Summary:
Hi Eric,

this patch cleans up the layering violation that you're fixing across backends.
Anything else I need to fix on bpf backend side?

Thanks

Reviewers: echristo

Reviewed By: echristo

Differential Revision: http://reviews.llvm.org/D7355

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227865 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoResurrect the assertion removed by r227717
Jingyue Wu [Mon, 2 Feb 2015 20:41:11 +0000 (20:41 +0000)]
Resurrect the assertion removed by r227717

Summary: MSVC can compile "LoopID->getOperand(0) == LoopID" when LoopID is MDNode*.

Test Plan: no regression

Reviewers: mkuper

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D7327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227853 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix the -Werror build, NFC
Duncan P. N. Exon Smith [Mon, 2 Feb 2015 20:20:56 +0000 (20:20 +0000)]
Fix the -Werror build, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227849 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Allow GenericDebugNode construction from MDString
Duncan P. N. Exon Smith [Mon, 2 Feb 2015 20:01:03 +0000 (20:01 +0000)]
IR: Allow GenericDebugNode construction from MDString

Allow `GenericDebugNode` construction directly from `MDString`, rather
than requiring `StringRef`s.  I've refactored the `StringRef`
constructors to use these.  There's no real functionality change here,
except for exposing the lower-level API.

The purpose of this is to simplify construction of string operands when
reading bitcode.  It's unnecessarily indirect to parse an `MDString` ID,
lookup the `MDString` in the bitcode reader list, get the `StringRef`
out of that, and then have `GenericDebugNode::getImpl()` use
`MDString::get()` to acquire the original `MDString`.  Instead, this
allows the bitcode reader to directly pass in the `MDString`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227848 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Extract DEFINE_MDNODE_GET(), NFC
Duncan P. N. Exon Smith [Mon, 2 Feb 2015 19:55:21 +0000 (19:55 +0000)]
IR: Extract DEFINE_MDNODE_GET(), NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227847 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Separate helpers for string operands, NFC
Duncan P. N. Exon Smith [Mon, 2 Feb 2015 19:54:05 +0000 (19:54 +0000)]
IR: Separate helpers for string operands, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227846 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Orc] Make OrcMCJITReplacement::addObject calls transfer buffer ownership to the
Lang Hames [Mon, 2 Feb 2015 19:51:18 +0000 (19:51 +0000)]
[Orc] Make OrcMCJITReplacement::addObject calls transfer buffer ownership to the
ObjectLinkingLayer.

There are a two of overloads for addObject, one of which transfers ownership of
the underlying buffer to OrcMCJITReplacement. This commit makes the ownership
transfering version pass ownership down to the ObjectLinkingLayer in order to
prevent the issue described in r227778.

I think this commit will fix the sanitizer bot failures that necessitated the
removal of the load-object-a.ll regression test in r227785, so I'm reinstating
that test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227845 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove simple case earlier and use a continue.
Rafael Espindola [Mon, 2 Feb 2015 19:22:51 +0000 (19:22 +0000)]
Move simple case earlier and use a continue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227841 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMigrate HexagonISelDAGToDAG to setting a subtarget pointer during
Eric Christopher [Mon, 2 Feb 2015 19:22:03 +0000 (19:22 +0000)]
Migrate HexagonISelDAGToDAG to setting a subtarget pointer during
runOnMachineFunction. Update all uses of the Subtarget accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227840 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse the getSubtarget call off of the MachineFunction rather than
Eric Christopher [Mon, 2 Feb 2015 19:22:01 +0000 (19:22 +0000)]
Use the getSubtarget call off of the MachineFunction rather than
the TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227839 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove unused class variables and update calls to get the subtarget
Eric Christopher [Mon, 2 Feb 2015 19:05:28 +0000 (19:05 +0000)]
Remove unused class variables and update calls to get the subtarget
off of the machine function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227837 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSink queries into asserts since the variable is unused otherwise.
Eric Christopher [Mon, 2 Feb 2015 18:58:24 +0000 (18:58 +0000)]
Sink queries into asserts since the variable is unused otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227836 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Split out DebugInfoMetadata.h, NFC
Duncan P. N. Exon Smith [Mon, 2 Feb 2015 18:53:21 +0000 (18:53 +0000)]
IR: Split out DebugInfoMetadata.h, NFC

Move debug-info-centred `Metadata` subclasses into their own
header/source file.  A couple of private template functions are needed
from both `Metadata.cpp` and `DebugInfoMetadata.cpp`, so I've moved them
to `lib/IR/MetadataImpl.h`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227835 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUpdate CMake build for removed files.
Eric Christopher [Mon, 2 Feb 2015 18:52:49 +0000 (18:52 +0000)]
Update CMake build for removed files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227834 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoGet TargetRegisterInfo and TargetInstrInfo off of the MachineFunction
Eric Christopher [Mon, 2 Feb 2015 18:46:31 +0000 (18:46 +0000)]
Get TargetRegisterInfo and TargetInstrInfo off of the MachineFunction
and remove unnecessary class variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227832 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse the function template getSubtarget to remove an explicit cast.
Eric Christopher [Mon, 2 Feb 2015 18:46:29 +0000 (18:46 +0000)]
Use the function template getSubtarget to remove an explicit cast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227831 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoGrab TargetInstrInfo off of the MachineFunction and remove
Eric Christopher [Mon, 2 Feb 2015 18:46:27 +0000 (18:46 +0000)]
Grab TargetInstrInfo off of the MachineFunction and remove
unnecessary class variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227830 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove unused files.
Eric Christopher [Mon, 2 Feb 2015 18:46:23 +0000 (18:46 +0000)]
Remove unused files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227829 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSTLExtras: Provide less/equal functors with templated function call operators, plus...
David Blaikie [Mon, 2 Feb 2015 18:35:10 +0000 (18:35 +0000)]
STLExtras: Provide less/equal functors with templated function call operators, plus a deref'ing functor template utility

Similar to the C++14 void specializations of these templates, useful as
a stop-gap until LLVM switches to '14.

Example use-cases in tblgen because I saw some functors that looked like
they could be simplified/refactored.

Reviewers: dexonsmith

Differential Revision: http://reviews.llvm.org/D7324

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227828 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDebug Info: Relax assertion in isUnsignedDIType() to allow floats to be
Adrian Prantl [Mon, 2 Feb 2015 18:31:58 +0000 (18:31 +0000)]
Debug Info: Relax assertion in isUnsignedDIType() to allow floats to be
described by integer constants. This is a bit ugly, but if the source
language allows arbitrary type casting, the debug info must follow suit.

For example:
  void foo() {
    float a;
    *(int *)&a = 0;
  }
For the curious: SROA replaces the float alloca with an i32 alloca, which
is then optimized away and described via dbg.value(i32 0, ...).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227827 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix some file headers, NFC
Duncan P. N. Exon Smith [Mon, 2 Feb 2015 18:20:15 +0000 (18:20 +0000)]
Fix some file headers, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227826 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSupport: Add missing header to BlockFrequencyTest.cpp, NFC
Duncan P. N. Exon Smith [Mon, 2 Feb 2015 18:18:07 +0000 (18:18 +0000)]
Support: Add missing header to BlockFrequencyTest.cpp, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227825 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: 64-bit and larger memory access must be at least 4-byte aligned
Tom Stellard [Mon, 2 Feb 2015 18:02:28 +0000 (18:02 +0000)]
R600/SI: 64-bit and larger memory access must be at least 4-byte aligned

This is true for SI only. CI+ supports unaligned memory accesses,
but this requires driver support, so for now we disallow unaligned
accesses for all GCN targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227822 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Merge two test files
Tom Stellard [Mon, 2 Feb 2015 18:02:23 +0000 (18:02 +0000)]
R600/SI: Merge two test files

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227821 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AArch64] Prefer DUP/MOV ("CPY") to INS for vector_extract.
Ahmed Bougacha [Mon, 2 Feb 2015 17:55:57 +0000 (17:55 +0000)]
[AArch64] Prefer DUP/MOV ("CPY") to INS for vector_extract.

This avoids a partial false dependency on the previous content of
the upper lanes of the destination vector register.

Differential Revision: http://reviews.llvm.org/D7307

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227820 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSince TargetLowering is already subtarget dependent just pass
Eric Christopher [Mon, 2 Feb 2015 17:52:27 +0000 (17:52 +0000)]
Since TargetLowering is already subtarget dependent just pass
in the subtarget and stash it in the class so that lookups are
easier and safer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227819 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse the function template getSubtarget on the MachineFunction
Eric Christopher [Mon, 2 Feb 2015 17:52:25 +0000 (17:52 +0000)]
Use the function template getSubtarget on the MachineFunction
rather than a larger explicit cast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227818 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove unused class variable.
Eric Christopher [Mon, 2 Feb 2015 17:52:23 +0000 (17:52 +0000)]
Remove unused class variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227817 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove unused class variable.
Eric Christopher [Mon, 2 Feb 2015 17:52:20 +0000 (17:52 +0000)]
Remove unused class variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227816 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agofix typo
Sanjay Patel [Mon, 2 Feb 2015 17:47:30 +0000 (17:47 +0000)]
fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227815 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReuse a bunch of cached subtargets and remove getSubtarget calls
Eric Christopher [Mon, 2 Feb 2015 17:38:43 +0000 (17:38 +0000)]
Reuse a bunch of cached subtargets and remove getSubtarget calls
without a Function argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227814 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove unnecessary forward declaration.
Eric Christopher [Mon, 2 Feb 2015 17:38:40 +0000 (17:38 +0000)]
Remove unnecessary forward declaration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227813 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove some unused forward declarations.
Eric Christopher [Mon, 2 Feb 2015 17:38:37 +0000 (17:38 +0000)]
Remove some unused forward declarations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227812 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix ARM peephole optimizeCompare to avoid optimizing unsigned cmp to 0.
Jan Wen Voung [Mon, 2 Feb 2015 16:56:50 +0000 (16:56 +0000)]
Fix ARM peephole optimizeCompare to avoid optimizing unsigned cmp to 0.

Summary:
Previously it only avoided optimizing signed comparisons to 0.
Sometimes the DAGCombiner will optimize the unsigned comparisons
to 0 before it gets to the peephole pass, but sometimes it doesn't.

Fix for PR22373.

Test Plan: test/CodeGen/ARM/sub-cmp-peephole.ll

Reviewers: jfb, manmanren

Subscribers: aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D7274

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227809 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix: SLPVectorizer crashes with assertion when vectorizing a cmp instruction.
Erik Eckstein [Mon, 2 Feb 2015 12:45:34 +0000 (12:45 +0000)]
Fix: SLPVectorizer crashes with assertion when vectorizing a cmp instruction.

The commit r225977 uncovered this bug. The problem was that the vectorizer tried to
read the second operand of an already deleted instruction.
The bug didn't show up before r225977 because the freed memory still contained a non-null pointer.
With r225977 deletion of instructions is delayed and the read operand pointer is always null.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227800 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Orc] Remove one of the OrcMCJITReplacement regression tests while I
Lang Hames [Mon, 2 Feb 2015 06:01:02 +0000 (06:01 +0000)]
[Orc] Remove one of the OrcMCJITReplacement regression tests while I
investigate a sanitizer bot failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227785 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agogold-plugin.cpp: Fixup r227599 corresponding to r227685 and r227731 -- Don't lose...
NAKAMURA Takumi [Mon, 2 Feb 2015 05:47:30 +0000 (05:47 +0000)]
gold-plugin.cpp: Fixup r227599 corresponding to r227685 and r227731 -- Don't lose DataLayoutPass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227783 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Orc] Regression tests for OrcMCJITReplacement.
Lang Hames [Mon, 2 Feb 2015 05:04:55 +0000 (05:04 +0000)]
[Orc] Regression tests for OrcMCJITReplacement.

Duplicated from the MCJIT regression tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227780 91177308-0d34-0410-b5e6-96231b3b80d8