oota-llvm.git
12 years agoSelect static relocation model if it is jitting.
Akira Hatanaka [Sat, 31 Mar 2012 02:38:36 +0000 (02:38 +0000)]
Select static relocation model if it is jitting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153795 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoIntroduce Register Units: Give each leaf register a number.
Andrew Trick [Sat, 31 Mar 2012 01:35:59 +0000 (01:35 +0000)]
Introduce Register Units: Give each leaf register a number.

First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153794 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a 2 byte safety margin in offset computations.
Jakob Stoklund Olesen [Sat, 31 Mar 2012 00:06:44 +0000 (00:06 +0000)]
Add a 2 byte safety margin in offset computations.

ARMConstantIslandPass still has bugs where jump table compression can
cause constant pool entries to go out of range.

Add a safety margin of 2 bytes when placing constant islands, but use
the real max displacement for verification.

<rdar://problem/11156595>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153789 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd more debugging output to ARMConstantIslandPass.
Jakob Stoklund Olesen [Sat, 31 Mar 2012 00:06:42 +0000 (00:06 +0000)]
Add more debugging output to ARMConstantIslandPass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153788 91177308-0d34-0410-b5e6-96231b3b80d8

12 years ago* Set the scope attributes for the ASM symbol we added to be the value passed
Bill Wendling [Fri, 30 Mar 2012 23:26:06 +0000 (23:26 +0000)]
* Set the scope attributes for the ASM symbol we added to be the value passed
  into the function.
* Reorder some header files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153783 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRip out emission of the regIsInRegClass function for the asm printer.
Benjamin Kramer [Fri, 30 Mar 2012 23:13:40 +0000 (23:13 +0000)]
Rip out emission of the regIsInRegClass function for the asm printer.

It's slow, bloated and completely redundant with MCRegisterClass::contains.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153782 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM fix encoding fixup resolution for ldrd and friends.
Jim Grosbach [Fri, 30 Mar 2012 21:54:22 +0000 (21:54 +0000)]
ARM fix encoding fixup resolution for ldrd and friends.

The 8-bit payload is not contiguous in the opcode. Move the upper nibble
over 4 bits into the correct place.

rdar://11158641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse SequenceToOffsetTable in emitRegisterNameString.
Jakob Stoklund Olesen [Fri, 30 Mar 2012 21:12:52 +0000 (21:12 +0000)]
Use SequenceToOffsetTable in emitRegisterNameString.

This allows suffix sharing in register names. (AX is a suffix of EAX).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153777 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReapply 153764 and 153761 with a fix.
Jakob Stoklund Olesen [Fri, 30 Mar 2012 20:24:14 +0000 (20:24 +0000)]
Reapply 153764 and 153761 with a fix.

Use an explicit comparator instead of the default.

The sets are sorted, but not using the default comparator. Hopefully,
this will unbreak the Linux builders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153772 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRevert 153764 and 153761. They broke a --enable-optimized --enable-assertions
Rafael Espindola [Fri, 30 Mar 2012 20:09:06 +0000 (20:09 +0000)]
Revert 153764 and 153761. They broke a --enable-optimized --enable-assertions
--enable-expensive-checks build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153771 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM assembler should prefer non-aliases encoding of cmp.
Jim Grosbach [Fri, 30 Mar 2012 19:59:02 +0000 (19:59 +0000)]
ARM assembler should prefer non-aliases encoding of cmp.

When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM encoding for VSWP got the second operand incorrect.
Jim Grosbach [Fri, 30 Mar 2012 18:53:01 +0000 (18:53 +0000)]
ARM encoding for VSWP got the second operand incorrect.

Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM can only use narrow encoding for low regs.
Jim Grosbach [Fri, 30 Mar 2012 18:39:43 +0000 (18:39 +0000)]
ARM can only use narrow encoding for low regs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153765 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCompress SimpleValueType lists by sharing.
Jakob Stoklund Olesen [Fri, 30 Mar 2012 17:42:04 +0000 (17:42 +0000)]
Compress SimpleValueType lists by sharing.

Many register classes have the same value types. Share the table space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153764 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCompress register lists by sharing suffixes.
Jakob Stoklund Olesen [Fri, 30 Mar 2012 17:25:43 +0000 (17:25 +0000)]
Compress register lists by sharing suffixes.

TableGen emits lists of sub-registers, super-registers, and overlaps. Put
them all in a single table and use a SequenceToOffsetTable to share
suffixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153761 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a SequenceToOffsetTable to TableGen.
Jakob Stoklund Olesen [Fri, 30 Mar 2012 17:25:40 +0000 (17:25 +0000)]
Add a SequenceToOffsetTable to TableGen.

This is similar to the StringToOffsetTable we use to produce string
tables, but it can be used for other sequences than strings, and it
eliminates entries for suffixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153760 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM integrated assembler should encoding choice for add/sub imm.
Jim Grosbach [Fri, 30 Mar 2012 17:20:40 +0000 (17:20 +0000)]
ARM integrated assembler should encoding choice for add/sub imm.

For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.

rdar://11156277

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoHandle unreachable code in the dominates functions. This changes users when
Rafael Espindola [Fri, 30 Mar 2012 16:46:21 +0000 (16:46 +0000)]
Handle unreachable code in the dominates functions. This changes users when
needed for correctness, but still doesn't clean up code that now unnecessary
checks for reachability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153755 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRe-factored RuntimeDyLd:
Danil Malyshev [Fri, 30 Mar 2012 16:45:19 +0000 (16:45 +0000)]
Re-factored RuntimeDyLd:

1. The main works will made in the RuntimeDyLdImpl with uses the ObjectFile class. RuntimeDyLdMachO and RuntimeDyLdELF now only parses relocations and resolve it. This is allows to make improvements of the RuntimeDyLd more easily. In addition the support for COFF can be easily added.

2. Added ARM relocations to RuntimeDyLdELF.

3. Added support for stub functions for the ARM, allowing to do a long branch.

4. Added support for external functions that are not loaded from the object files, but can be loaded from external libraries. Now MCJIT can correctly execute the code containing the printf, putc, and etc.

5. The sections emitted instead functions, thanks Jim Grosbach. MemoryManager.startFunctionBody() and MemoryManager.endFunctionBody() have been removed.
6. MCJITMemoryManager.allocateDataSection() and MCJITMemoryManager. allocateCodeSection() used JMM->allocateSpace() instead of JMM->allocateCodeSection() and JMM->allocateDataSection(), because I got an error: "Cannot allocate an allocated block!" with object file contains more than one code or data sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153754 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM assembly parsing needs to be paranoid about negative immediates.
Jim Grosbach [Fri, 30 Mar 2012 16:31:31 +0000 (16:31 +0000)]
ARM assembly parsing needs to be paranoid about negative immediates.

Make sure to treat immediates as unsigned when doing relative comparisons.

rdar://11153621

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd computeMaskedBitsLoad back, as it was the change to instsimplify that
Rafael Espindola [Fri, 30 Mar 2012 15:52:11 +0000 (15:52 +0000)]
Add computeMaskedBitsLoad back, as it was the change to instsimplify that
caused the slowdown last time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153747 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a note about a missed cmov -> sbb opportunity.
Benjamin Kramer [Fri, 30 Mar 2012 13:02:58 +0000 (13:02 +0000)]
Add a note about a missed cmov -> sbb opportunity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153741 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCleanup whitespace. Doxygenize comments. And indent to llvm coding standards.
Bill Wendling [Fri, 30 Mar 2012 10:29:38 +0000 (10:29 +0000)]
Cleanup whitespace. Doxygenize comments. And indent to llvm coding standards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153740 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnsure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
James Molloy [Fri, 30 Mar 2012 09:15:32 +0000 (09:15 +0000)]
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.

Patch by Tim Northover!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM target should allow codegenprep to duplicate ret instructions to enable tailcall...
Evan Cheng [Fri, 30 Mar 2012 01:24:39 +0000 (01:24 +0000)]
ARM target should allow codegenprep to duplicate ret instructions to enable tailcall opt. rdar://11140249

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTestcase for r153710.
Bill Wendling [Fri, 30 Mar 2012 00:26:54 +0000 (00:26 +0000)]
Testcase for r153710.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153711 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd testcase for r153705
Bill Wendling [Fri, 30 Mar 2012 00:05:02 +0000 (00:05 +0000)]
Add testcase for r153705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153706 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoIf we have a VLA that has a "use" in a metadata node that's then used
Bill Wendling [Fri, 30 Mar 2012 00:02:55 +0000 (00:02 +0000)]
If we have a VLA that has a "use" in a metadata node that's then used
here but it has no other uses, then we have a problem. E.g.,

  int foo (const int *x) {
    char a[*x];
    return 0;
  }

If we assign 'a' a vreg and fast isel later on has to use the selection
DAG isel, it will want to copy the value to the vreg. However, there are
no uses, which goes counter to what selection DAG isel expects.
<rdar://problem/11134152>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153705 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoChange the constant in this testcase so that it results in a constant pool
Lang Hames [Thu, 29 Mar 2012 23:52:38 +0000 (23:52 +0000)]
Change the constant in this testcase so that it results in a constant pool
load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153704 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRevert r153694. It was causing failures in the buildbots.
Bill Wendling [Thu, 29 Mar 2012 23:23:59 +0000 (23:23 +0000)]
Revert r153694. It was causing failures in the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153701 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoInvalidate liveness in ARMConstantIslandPass.
Jakob Stoklund Olesen [Thu, 29 Mar 2012 23:14:26 +0000 (23:14 +0000)]
Invalidate liveness in ARMConstantIslandPass.

This pass splits basic blocks to insert constant islands, and it
doesn't recompute the live-in lists. No later passes depend on accurate
liveness information.

This fixes PR12410 where the machine code verifier was complaining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153700 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoPrefer even-odd D-register pairs.
Jakob Stoklund Olesen [Thu, 29 Mar 2012 22:54:32 +0000 (22:54 +0000)]
Prefer even-odd D-register pairs.

We are sometimes allocatinog from the DPair register class which
contains odd-even pairs in addition to the Q registers.

Place the Q registers first in the DPair allocation order as they can be
copied with a single instruction. The odd-even pairs should only be
allocated as a last resort.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153699 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFilecheck-ize this test so that it actually tests something reasonable.
Chandler Carruth [Thu, 29 Mar 2012 22:01:41 +0000 (22:01 +0000)]
Filecheck-ize this test so that it actually tests something reasonable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153697 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTry using vmov.i32 to materialize FP32 constants that can't be materialized by
Lang Hames [Thu, 29 Mar 2012 21:56:11 +0000 (21:56 +0000)]
Try using vmov.i32 to materialize FP32 constants that can't be materialized by
vmov.f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153696 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRe-factored RuntimeDyld.
Danil Malyshev [Thu, 29 Mar 2012 21:46:18 +0000 (21:46 +0000)]
Re-factored RuntimeDyld.
Added ExecutionEngine/MCJIT tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153694 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoLowercase the tag name to match the rest of dwarf.
Eric Christopher [Thu, 29 Mar 2012 21:35:05 +0000 (21:35 +0000)]
Lowercase the tag name to match the rest of dwarf.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153691 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARM assembly 'cmp lr, #0' should not encode using 'cmn'.
Jim Grosbach [Thu, 29 Mar 2012 21:19:52 +0000 (21:19 +0000)]
ARM assembly 'cmp lr, #0' should not encode using 'cmn'.

The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.

rdar://11129224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoThe shuffle scheduler is only available in asserts build - make misched-new.ll
Lang Hames [Thu, 29 Mar 2012 21:11:47 +0000 (21:11 +0000)]
The shuffle scheduler is only available in asserts build - make misched-new.ll
testcase require asserts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153687 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoHandle register copies for the new ARM register classes.
Jakob Stoklund Olesen [Thu, 29 Mar 2012 21:10:40 +0000 (21:10 +0000)]
Handle register copies for the new ARM register classes.

ARM recently gained DPair, DTriple, and DQuad register classes.
Update copyPhysReg() to handle copies in these register classes.

No test case, it is difficult to make the register allocator emit the
odd copies reliably. The missing DPair copy caused a failure on
partialsums in the nightly test suite.

<rdar://problem/11147997>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153686 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDrop O4 from the llc manpage, it was removed in r70445.
Benjamin Kramer [Thu, 29 Mar 2012 20:40:18 +0000 (20:40 +0000)]
Drop O4 from the llc manpage, it was removed in r70445.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153684 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMake x86 REP_MOV* and REP_STO instructions use the correct operand sizes in 64-bit...
Lang Hames [Thu, 29 Mar 2012 19:54:28 +0000 (19:54 +0000)]
Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in 64-bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153680 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix missed files in JIT unittests Makefile
Danil Malyshev [Thu, 29 Mar 2012 18:53:15 +0000 (18:53 +0000)]
Fix missed files in JIT unittests Makefile

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153672 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoExpand FREM.
Akira Hatanaka [Thu, 29 Mar 2012 18:43:11 +0000 (18:43 +0000)]
Expand FREM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153671 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd more constness to CodeGenRegisters.
Jakob Stoklund Olesen [Thu, 29 Mar 2012 18:03:59 +0000 (18:03 +0000)]
Add more constness to CodeGenRegisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153667 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDon't PRE compares.
Jakob Stoklund Olesen [Thu, 29 Mar 2012 17:22:39 +0000 (17:22 +0000)]
Don't PRE compares.

CodeGenPrepare sinks compare instructions down to their uses to prevent
live flags and predicate registers across basic blocks.

PRE of a compare instruction prevents that, forcing the i1 compare
result into a general purpose register.  That is usually more expensive
than the redundant compare PRE was trying to eliminate in the first
place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153657 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReplace assert(0) with llvm_unreachable to avoid warnings about dropping off the...
Benjamin Kramer [Thu, 29 Mar 2012 12:37:26 +0000 (12:37 +0000)]
Replace assert(0) with llvm_unreachable to avoid warnings about dropping off the end of a non-void function in Release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153643 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd support for objc property decls according to the page at:
Eric Christopher [Thu, 29 Mar 2012 08:42:56 +0000 (08:42 +0000)]
Add support for objc property decls according to the page at:

http://llvm.org/docs/SourceLevelDebugging.html#objcproperty

including type and DECL. Expand the metadata needed accordingly.

rdar://11144023

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153639 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMake some headway towards compiling all of LLVM.
Bill Wendling [Thu, 29 Mar 2012 08:27:32 +0000 (08:27 +0000)]
Make some headway towards compiling all of LLVM.

Module-level ASM may contain definitions of functions and globals. However, we
were not telling the linker that these globals had definitions. As far as it was
concerned, they were just declarations.

Attempt to resolve this by inserting module-level ASM functions and globals into
the '_symbol' set so that the linker will know that they have values.

This gets us further towards our goal of compiling LLVM, but it still has
problems when linking libLTO.dylib because of the `-dead_strip' flag that's
passed to the linker.

<rdar://problem/11124216>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153638 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoOnly allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used with 'v...
Craig Topper [Thu, 29 Mar 2012 07:11:23 +0000 (07:11 +0000)]
Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used with 'v' version of instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153636 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFor X86, change load/dec-or-inc/store into dec-or-inc, respectively.
Joel Jones [Thu, 29 Mar 2012 05:45:48 +0000 (05:45 +0000)]
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.

This is a code change to add support for changing instruction sequences of the form:

  load
  inc/dec of 8/16/32/64 bits
  store

into the appropriate X86 inc/dec through memory instruction:

  inc[qlwb] / dec[qlwb]

The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode.  The comments have also been expanded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153635 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCleanup whitespace.
Bill Wendling [Thu, 29 Mar 2012 04:28:00 +0000 (04:28 +0000)]
Cleanup whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153634 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCache the end() iterator.
Bill Wendling [Thu, 29 Mar 2012 03:34:57 +0000 (03:34 +0000)]
Cache the end() iterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153632 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReverted to revision 153616 to unblock build
Joel Jones [Thu, 29 Mar 2012 01:20:56 +0000 (01:20 +0000)]
Reverted to revision 153616 to unblock build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153623 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFor X86, change load/dec-or-inc/store into dec-or-inc, respectively.
Joel Jones [Thu, 29 Mar 2012 00:37:47 +0000 (00:37 +0000)]
For X86, change load/dec-or-inc/store into dec-or-inc, respectively.

This is a code change to add support for changing instruction sequences of the form:

  load
  inc/dec of 8/16/32/64 bits
  store

into the appropriate X86 inc/dec through memory instruction:

  inc[qlwb] / dec[qlwb]

The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better
named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode.  The comments have also been expanded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153617 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable machine code verification in the entire code generator.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 23:54:28 +0000 (23:54 +0000)]
Enable machine code verification in the entire code generator.

Some targets still mess up the liveness information, but that isn't
verified after MRI->invalidateLiveness().

The verifier can still check other useful things like register classes
and CFG, so it should be enabled after all passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153615 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable machine code verification after PreSched2 passes.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 23:31:15 +0000 (23:31 +0000)]
Enable machine code verification after PreSched2 passes.

The late scheduler depends on accurate liveness information if it is
breaking anti-dependencies, so we should be able to verify it.

Relax the terminator checking in the machine code verifier so it can
handle the basic blocks created by if conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153614 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoCleanup some whitespaces.
Bill Wendling [Wed, 28 Mar 2012 23:12:18 +0000 (23:12 +0000)]
Cleanup some whitespaces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153612 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoDon't kill the base register when expanding strd.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 23:07:03 +0000 (23:07 +0000)]
Don't kill the base register when expanding strd.

When an strd instruction doesn't get the registers it wants, it can be
expanded into two str instructions. Make sure the first str doesn't kill
the base register in the case where the base and data registers are
identical:

  t2STRi12 %R0<kill>, %R0, 4, pred:14, pred:%noreg
  t2STRi12 %R2<kill>, %R0, 8, pred:14, pred:%noreg

<rdar://problem/11101911>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153611 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoPreserve implicit defs in ARMLoadStoreOptimizer.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 22:50:56 +0000 (22:50 +0000)]
Preserve implicit defs in ARMLoadStoreOptimizer.

When a number of sub-register VLRDS instructions are combined into a
VLDM, preserve any super-register implicit defs. This is required to
keep the register scavenger and machine code verifier happy.

Enable machine code verification after ARMLoadStoreOptimizer.
ARM/2012-01-26-CopyPropKills.ll was failing because of this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153610 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTidy up. Whitespace.
Jim Grosbach [Wed, 28 Mar 2012 22:34:41 +0000 (22:34 +0000)]
Tidy up. Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153609 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMove getPointerToNamedFunction() from JIT/MCJIT to JITMemoryManager.
Danil Malyshev [Wed, 28 Mar 2012 21:46:36 +0000 (21:46 +0000)]
Move getPointerToNamedFunction() from JIT/MCJIT to JITMemoryManager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153607 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoHandle intrinsics in GlobalsModRef. Fixes pr12351.
Rafael Espindola [Wed, 28 Mar 2012 21:31:24 +0000 (21:31 +0000)]
Handle intrinsics in GlobalsModRef. Fixes pr12351.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153604 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSpill DPair registers, not just QPR.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 21:20:32 +0000 (21:20 +0000)]
Spill DPair registers, not just QPR.

The arm_neon intrinsics can create virtual registers from the DPair
register class which allows both even-odd and odd-even D-register pairs.

This fixes PR12389.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153603 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAlso verify after ExpandPostRAPseudos.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 20:49:30 +0000 (20:49 +0000)]
Also verify after ExpandPostRAPseudos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153599 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoInline function into its one caller.
Bill Wendling [Wed, 28 Mar 2012 20:48:49 +0000 (20:48 +0000)]
Inline function into its one caller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153598 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEnable machine code verification after the late machine optimization passes.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 20:47:37 +0000 (20:47 +0000)]
Enable machine code verification after the late machine optimization passes.

Branch folding invalidates liveness and disables liveness verification
on some targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153597 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSkip liveness verification when MRI->tracksLiveness() is false.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 20:47:35 +0000 (20:47 +0000)]
Skip liveness verification when MRI->tracksLiveness() is false.

Extract the liveness verification into its own method.

This makes it possible to run the machine code verifier after liveness
information is no longer required to be valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153596 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReformat the LTOModule code to be more inline with LLVM's coding standards. Add
Bill Wendling [Wed, 28 Mar 2012 20:46:54 +0000 (20:46 +0000)]
Reformat the LTOModule code to be more inline with LLVM's coding standards. Add
a bunch of comments for the various functions. No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153595 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRevert r153516: "Invalidate liveness in Thumb2ITBlockPass."
Jakob Stoklund Olesen [Wed, 28 Mar 2012 20:11:44 +0000 (20:11 +0000)]
Revert r153516: "Invalidate liveness in Thumb2ITBlockPass."
Revert r153519: "ARMLoadStoreOptimizer invalidates register liveness."

These patches caused miscompilations in povray by turning off branch
folding's updating of live-in lists.

It turns out the the late scheduler depends on the live-in lists, even
if it doesn't need correct kill flags.

<rdar://problem/11139228>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153593 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAllow removeLiveIn to be called with a register that isn't live-in.
Jakob Stoklund Olesen [Wed, 28 Mar 2012 20:11:42 +0000 (20:11 +0000)]
Allow removeLiveIn to be called with a register that isn't live-in.

This avoids the silly double search:

  if (isLiveIn(Reg))
    removeLiveIn(Reg);

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153592 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRevert r153521 as it's causing large regressions on the nightly testers.
Chad Rosier [Wed, 28 Mar 2012 18:42:50 +0000 (18:42 +0000)]
Revert r153521 as it's causing large regressions on the nightly testers.
Original commit message for r153521 (aka r153423):
Use the new range metadata in computeMaskedBits and add a new optimization to
instruction simplify that lets us remove an and when loding a boolean value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153587 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFixed commuteInstructions bug where if its called pre-regalloc the subreg indices...
Pete Cooper [Wed, 28 Mar 2012 17:02:22 +0000 (17:02 +0000)]
Fixed commuteInstructions bug where if its called pre-regalloc the subreg indices weren't commuted

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153579 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoGlobalOpt: If we have an inbounds GEP from a ConstantAggregateZero global that we...
Benjamin Kramer [Wed, 28 Mar 2012 14:50:09 +0000 (14:50 +0000)]
GlobalOpt: If we have an inbounds GEP from a ConstantAggregateZero global that we just determined to be constant, replace all loads from it with a zero value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153576 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd another note about a missed compare with nsw arithmetic instcombine.
Benjamin Kramer [Wed, 28 Mar 2012 10:50:18 +0000 (10:50 +0000)]
Add another note about a missed compare with nsw arithmetic instcombine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153574 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFixup VST1.32 with writeback instruction. Also re-factor non-writeback version.
Richard Barton [Wed, 28 Mar 2012 10:18:11 +0000 (10:18 +0000)]
Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153573 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSwitch to WeakVHs in the value mapper, and aggressively prune dead basic
Chandler Carruth [Wed, 28 Mar 2012 08:38:27 +0000 (08:38 +0000)]
Switch to WeakVHs in the value mapper, and aggressively prune dead basic
blocks in the function cloner. This removes the last case of trivially
dead code that I've been seeing in the wild getting inlined, analyzed,
re-inlined, optimized, only to be deleted. Nukes a FIXME from the
cleanup tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153572 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMore debug output.
Eric Christopher [Wed, 28 Mar 2012 07:34:36 +0000 (07:34 +0000)]
More debug output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153571 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix the output of the DW_TAG_friend tag to include DW_AT_friend
Eric Christopher [Wed, 28 Mar 2012 07:34:31 +0000 (07:34 +0000)]
Fix the output of the DW_TAG_friend tag to include DW_AT_friend
and not the rest of the member tag.

Fixes PR11695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153570 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSome whitespace cleanup.
Bill Wendling [Wed, 28 Mar 2012 04:17:34 +0000 (04:17 +0000)]
Some whitespace cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153567 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse the correct filename for the error message.
Bill Wendling [Wed, 28 Mar 2012 02:39:06 +0000 (02:39 +0000)]
Use the correct filename for the error message.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153564 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse Nakamura's suggestion of bypassing using 'filename' and just the pointers directly.
Bill Wendling [Wed, 28 Mar 2012 01:30:51 +0000 (01:30 +0000)]
Use Nakamura's suggestion of bypassing using 'filename' and just the pointers directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153558 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTurn off post-RA scheduler by default.
Akira Hatanaka [Wed, 28 Mar 2012 00:52:23 +0000 (00:52 +0000)]
Turn off post-RA scheduler by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153557 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix 80-column violation.
Chad Rosier [Wed, 28 Mar 2012 00:35:33 +0000 (00:35 +0000)]
Fix 80-column violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153556 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoFix test case.
Akira Hatanaka [Wed, 28 Mar 2012 00:25:01 +0000 (00:25 +0000)]
Fix test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153555 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTurn on post register allocation scheduler.
Akira Hatanaka [Wed, 28 Mar 2012 00:24:17 +0000 (00:24 +0000)]
Turn on post register allocation scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153554 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoSort relocation entries before they are written out to a file. MIPS ABI
Akira Hatanaka [Wed, 28 Mar 2012 00:23:33 +0000 (00:23 +0000)]
Sort relocation entries before they are written out to a file. MIPS ABI
imposes a constraint that GOT16 referring to a local symbol or HI16 has to be
followed immediately by a matching LO16 relocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153553 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoEmit all directives except for ".cprestore" during asm printing rather than emit
Akira Hatanaka [Wed, 28 Mar 2012 00:22:50 +0000 (00:22 +0000)]
Emit all directives except for ".cprestore" during asm printing rather than emit
them as machine instructions. Directives ".set noat" and ".set at" are now
emitted only at the beginning and end of a function except in the case where
they are emitted to enclose .cpload with an immediate operand that doesn't fit
in 16-bit field or unaligned load/stores.

Also, make the following changes:
- Remove function isUnalignedLoadStore and use a switch-case statement to
  determine whether an instruction is an unaligned load or store.

- Define helper function CreateMCInst which generates an instance of an MCInst
  from an opcode and a list of operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153552 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMark flag neverHasSideEffects of pattern-less instructions that do not have
Akira Hatanaka [Wed, 28 Mar 2012 00:21:37 +0000 (00:21 +0000)]
Mark flag neverHasSideEffects of pattern-less instructions that do not have
any side effects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153551 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoMSVC doesn't like the mixing of declarations and statements in a .c file.
Francois Pichet [Tue, 27 Mar 2012 23:52:22 +0000 (23:52 +0000)]
MSVC doesn't like the mixing of declarations and statements in a .c file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153549 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a note about a cute little fabs optimization.
Benjamin Kramer [Tue, 27 Mar 2012 22:42:42 +0000 (22:42 +0000)]
Add a note about a cute little fabs optimization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153543 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd two missed instcombines related to compares with nsw arithmetic.
Benjamin Kramer [Tue, 27 Mar 2012 22:03:19 +0000 (22:03 +0000)]
Add two missed instcombines related to compares with nsw arithmetic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153542 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoTry to use the CWD if the path to the GCDA output is not available (e.g., the
Bill Wendling [Tue, 27 Mar 2012 21:17:04 +0000 (21:17 +0000)]
Try to use the CWD if the path to the GCDA output is not available (e.g., the
executable has been moved to another machine). If that's not available
(read-only or something), then exit gracefully.
<rdar://problem/11111686>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153538 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoRemove trailing white space.
Akira Hatanaka [Tue, 27 Mar 2012 20:35:51 +0000 (20:35 +0000)]
Remove trailing white space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153536 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse a SmallVector and linear lookup instead of a DenseSet - SourceMap values
Lang Hames [Tue, 27 Mar 2012 19:10:45 +0000 (19:10 +0000)]
Use a SmallVector and linear lookup instead of a DenseSet - SourceMap values
will always be tiny sets, so DenseSet is overkill (SmallSet won't work as we
need iteration support).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153529 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd member EmitNOAT and its setter and getter functions to class MipsFunctionInfo.
Akira Hatanaka [Tue, 27 Mar 2012 19:08:42 +0000 (19:08 +0000)]
Add member EmitNOAT and its setter and getter functions to class MipsFunctionInfo.
If EmitNOAT is true, directives ".set noat" and ".set at" are emitted at the
beginning and end of a function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153528 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoAdd a test for the previous commit. Also, remove two tests that were
Eric Christopher [Tue, 27 Mar 2012 18:35:57 +0000 (18:35 +0000)]
Add a test for the previous commit. Also, remove two tests that were
testing a) the wrong behavior or b) something that I'm already testing
in the new test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153525 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoUse DW_AT_low_pc for a single entry point into a routine.
Eric Christopher [Tue, 27 Mar 2012 18:35:54 +0000 (18:35 +0000)]
Use DW_AT_low_pc for a single entry point into a routine.

Fixes PR10105

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153524 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoReapply r153423; the original commit was fine. The failing test, distray, had
Chad Rosier [Tue, 27 Mar 2012 17:44:52 +0000 (17:44 +0000)]
Reapply r153423; the original commit was fine.  The failing test, distray, had
undefined behavior, which Rafael was kind enough to fix.

Original commit message for r153423:
Use the new range metadata in computeMaskedBits and add a new optimization to
instruction simplify that lets us remove an and when loding a boolean value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153521 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoARMLoadStoreOptimizer invalidates register liveness.
Jakob Stoklund Olesen [Tue, 27 Mar 2012 17:33:52 +0000 (17:33 +0000)]
ARMLoadStoreOptimizer invalidates register liveness.

This pass tries to update kill flags, but there are still many bugs.
Passes after the load/store optimizer don't need accurate liveness, so
don't even try.

<rdar://problem/11101911>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153519 91177308-0d34-0410-b5e6-96231b3b80d8

12 years agoPrint SSA and liveness tracking flags in MF::print().
Jakob Stoklund Olesen [Tue, 27 Mar 2012 17:17:16 +0000 (17:17 +0000)]
Print SSA and liveness tracking flags in MF::print().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153518 91177308-0d34-0410-b5e6-96231b3b80d8