oota-llvm.git
9 years ago[InstCombine] Properly combine metadata when replacing a load with another
Bjorn Steinbrink [Fri, 10 Jul 2015 06:55:44 +0000 (06:55 +0000)]
[InstCombine] Properly combine metadata when replacing a load with another

Not doing this can lead to misoptimizations down the line, e.g. because
of range metadata on the replacing load excluding values that are valid
for the load that is being replaced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241886 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[NVPTX] declare no vector registers
Jingyue Wu [Fri, 10 Jul 2015 04:31:56 +0000 (04:31 +0000)]
[NVPTX] declare no vector registers

Summary:
Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll)
produces code with complex control flow which hurts later optimizations. Since
NVPTX doesn't have vector registers in LLVM's sense
(NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector
registers to effectively disable loop vectorization.

Reviewers: jholewinski

Subscribers: jingyue, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11089

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241884 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Make sure LSDA tables are 4 byte aligned
Reid Kleckner [Fri, 10 Jul 2015 00:08:49 +0000 (00:08 +0000)]
[WinEH] Make sure LSDA tables are 4 byte aligned

Apparently this is important, otherwise _except_handler3 assumes that
the registration node is corrupted and ignores it.

Also fix a bug in WinEHPrepare where we would insert code after a
terminator instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241877 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReplace index-loops by range-based loops
Eli Bendersky [Thu, 9 Jul 2015 23:06:03 +0000 (23:06 +0000)]
Replace index-loops by range-based loops

NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241875 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] enable machine combiner reassociations for scalar double-precision multiplies
Sanjay Patel [Thu, 9 Jul 2015 22:58:39 +0000 (22:58 +0000)]
[x86] enable machine combiner reassociations for scalar double-precision multiplies

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241873 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] enable machine combiner reassociations for scalar double-precision adds
Sanjay Patel [Thu, 9 Jul 2015 22:48:54 +0000 (22:48 +0000)]
[x86] enable machine combiner reassociations for scalar double-precision adds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241871 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix shadowing.
Michael J. Spencer [Thu, 9 Jul 2015 22:42:21 +0000 (22:42 +0000)]
Fix shadowing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241870 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Object][ELF] Support dumping hash-tables from files with no section table.
Michael J. Spencer [Thu, 9 Jul 2015 22:32:24 +0000 (22:32 +0000)]
[Object][ELF] Support dumping hash-tables from files with no section table.

This time without breaking the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241869 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMIR Serialization: Serialize the virtual register definitions.
Alex Lorenz [Thu, 9 Jul 2015 22:23:13 +0000 (22:23 +0000)]
MIR Serialization: Serialize the virtual register definitions.

The virtual registers are serialized using a YAML sequence of YAML inline
mappings. Each mapping has the id of the virtual register and the register
class.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10981

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241868 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LAA] Fix grammar in debug output
Adam Nemet [Thu, 9 Jul 2015 22:17:41 +0000 (22:17 +0000)]
[LAA] Fix grammar in debug output

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241867 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LAA] Hide NeedRTCheck logic completely inside canCheckPtrAtRT, NFC
Adam Nemet [Thu, 9 Jul 2015 22:17:38 +0000 (22:17 +0000)]
[LAA] Hide NeedRTCheck logic completely inside canCheckPtrAtRT, NFC

Currently canCheckPtrAtRT returns two flags NeedRTCheck and CanDoRT.
NeedRTCheck says whether we need checks and CanDoRT whether we can
generate the checks.  The idea is to encode three states with these:

     Need/Can:
(1) false/dont-care: no checks are needed
(2) true/false: we need checks but can't generate them
(3) true/true: we need checks and we can generate them

This is pretty unnecessary since the caller (analyzeLoop) is only
interested in whether we can generate the checks if we actually need
them (i.e. 1 or 3).

So this change cleans up to return just that (CanDoRTIfNeeded) and pulls
all the underlying logic into canCheckPtrAtRT.

By doing all this, we simplify analyzeLoop which is the complex function
in LAA.

There is further room for improvement here by using RtCheck.Need
directly rather than a new local variable NeedRTCheck but that's for a
later patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241866 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Give up on using CSRs across 32-bit invokes for now
Reid Kleckner [Thu, 9 Jul 2015 22:09:41 +0000 (22:09 +0000)]
[WinEH] Give up on using CSRs across 32-bit invokes for now

The runtime does not restore CSRs when transferring control back to the
function handling the exception. According to the experts on IRC, LLVM's
register allocator has no way to model register clobbers that only
happen on one edge of the CFG. For now, don't worry about trying to use
the meager three CSRs available on 32-bit X86 and just say that such
invokes preserve nothing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241865 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoExpose sjlj preparation through opt for my own debugging purposes
Reid Kleckner [Thu, 9 Jul 2015 21:48:40 +0000 (21:48 +0000)]
Expose sjlj preparation through opt for my own debugging purposes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241864 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMIR Parser: Report an error when parsing machine function with an empty body.
Alex Lorenz [Thu, 9 Jul 2015 21:21:33 +0000 (21:21 +0000)]
MIR Parser: Report an error when parsing machine function with an empty body.

This commit adds a new error which is reported when the MIR Parser encounters
a machine function without any machine basic blocks. The machine verifier
expects that the machine functions have at least one MBB, and this error will
prevent machine functions without MBBs from reaching the machine verifier and
crashing with an assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241862 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAMDGPU: Add helper function for implicit parameter offsets.
Tom Stellard [Thu, 9 Jul 2015 21:20:37 +0000 (21:20 +0000)]
AMDGPU: Add helper function for implicit parameter offsets.

Patch by: Zoltan Gilian

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241861 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUnbreak WebAssembly build
JF Bastien [Thu, 9 Jul 2015 21:00:09 +0000 (21:00 +0000)]
Unbreak WebAssembly build

Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed.

Reviewers: sunfish, joker.eph, echristo

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241859 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoWebAssembly: add placeholder intrinsics header
JF Bastien [Thu, 9 Jul 2015 20:57:38 +0000 (20:57 +0000)]
WebAssembly: add placeholder intrinsics header

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11080

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241858 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ImplicitNullChecks] Fix a memory leak.
Sanjoy Das [Thu, 9 Jul 2015 20:13:31 +0000 (20:13 +0000)]
[ImplicitNullChecks] Fix a memory leak.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241851 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ImplicitNullChecks] Be smarter in picking the memory op.
Sanjoy Das [Thu, 9 Jul 2015 20:13:25 +0000 (20:13 +0000)]
[ImplicitNullChecks] Be smarter in picking the memory op.

Summary:
Before this change ImplicitNullChecks would only pick loads of the form:

```
   test Reg, Reg
   jz elsewhere
 fallthrough:
   movl 32(Reg), Reg2
```

but not (say)

```
   test Reg, Reg
   jz elsewhere
 fallthrough:
   inc Reg3
   movl 32(Reg), Reg2
```

This change teaches ImplicitNullChecks to look through "unrelated"
instructions like `inc Reg3` when searching for a load instruction
to convert to a trapping load.

Reviewers: atrick, JosephTremoulet, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241850 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoCreate BSD archives by default on OS X.
Rafael Espindola [Thu, 9 Jul 2015 20:12:50 +0000 (20:12 +0000)]
Create BSD archives by default on OS X.

They should probably be created on anything that is not windows or linux, but I will
test on freebsd before changing that.

With this it is possible to bootstrap with llvm-ar instead of ar+ranlib on OS X.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241849 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMIR Serialization: Serialize the simple MachineFrameInfo attributes.
Alex Lorenz [Thu, 9 Jul 2015 19:55:27 +0000 (19:55 +0000)]
MIR Serialization: Serialize the simple MachineFrameInfo attributes.

This commit serializes the 13 scalar boolean and integer attributes from the
MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap,
HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack,
HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and
HasMustTailInVarArgFunc. These attributes are serialized as part
of the frameInfo YAML mapping, which itself is a part of the machine function's
YAML mapping.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241844 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agollvm-ar: Pad the symbol table to 4 bytes.
Rafael Espindola [Thu, 9 Jul 2015 19:48:06 +0000 (19:48 +0000)]
llvm-ar: Pad the symbol table to 4 bytes.

It looks like ld64 requires it. With this we seem to be able to bootstrap using
llvm-ar+/usr/bin/true instead of ar+ranlib (currently on stage2).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241842 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAMDGPU/R600: Return correct chain when lowering loads
Matt Arsenault [Thu, 9 Jul 2015 18:47:03 +0000 (18:47 +0000)]
AMDGPU/R600: Return correct chain when lowering loads

The other LowerLOAD should be returning the correct chain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241839 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[IndVars] Try to use existing values in RewriteLoopExitValues.
Sanjoy Das [Thu, 9 Jul 2015 18:46:12 +0000 (18:46 +0000)]
[IndVars] Try to use existing values in RewriteLoopExitValues.

Summary:
In RewriteLoopExitValues, before expanding out an SCEV expression using
SCEVExpander, try to see if an existing LLVM IR expression already
computes the value we're interested in.  If so use that existing
expression.

Apart from reducing IndVars' reliance on the rest of the compilation
pipeline, this also prevents IndVars from concluding some expressions as
"high cost" when they're not.  For instance,
`InductiveRangeCheckElimination` often emits code of the following form:

```
len = umin(len_A, len_B)

loop:
  ...
  if (i++ < len)
    goto loop

outside_loop:
    use(i)
```

`SCEVExpander` refuses to rewrite the use of `i` in `outside_loop`,
since it thinks the value of `i` on loop exit, `len`, is a high cost
expansion since it contains an `umax` in it.  With this change,
`IndVars` can see that it can re-use `len` instead of creating a new
expression to compute `umin(len_A, len_B)`.

I considered putting this cleverness in `SCEVExpander`, but I was
worried that it may then have a deterimental effect on other passes
that use it.  So I decided it was better to just do this in the one
place where it seems like an obviously good idea, with the intent of
generalizing later if needed.

Reviewers: atrick, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10782

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241838 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[llvm-readobj] Print MIPS PLT table
Simon Atanasyan [Thu, 9 Jul 2015 18:23:10 +0000 (18:23 +0000)]
[llvm-readobj] Print MIPS PLT table

Now the -mips-plt-got prints both MIPS GOT and PLT tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241836 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[yaml2obj] Initialize sh_addralign field for the .symtab section
Simon Atanasyan [Thu, 9 Jul 2015 18:23:02 +0000 (18:23 +0000)]
[yaml2obj] Initialize sh_addralign field for the .symtab section

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241835 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ELF] Explicitly configure sections alignment in the tests. NFC
Simon Atanasyan [Thu, 9 Jul 2015 18:22:55 +0000 (18:22 +0000)]
[ELF] Explicitly configure sections alignment in the tests. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241834 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[llvm-readobj] Re-add sanity checking which was accidentally removed in r241764
David Majnemer [Thu, 9 Jul 2015 18:14:31 +0000 (18:14 +0000)]
[llvm-readobj] Re-add sanity checking which was accidentally removed in r241764

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241831 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[llvm-objdump] Require that jump targets shown in -d are functions
David Majnemer [Thu, 9 Jul 2015 18:11:40 +0000 (18:11 +0000)]
[llvm-objdump] Require that jump targets shown in -d are functions

Don't let the disassembler pick call <.text> if a function happens to
live at the start of the section by only using function symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241830 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove dead code from old 64-bit SEH lowering
Reid Kleckner [Thu, 9 Jul 2015 17:46:39 +0000 (17:46 +0000)]
Remove dead code from old 64-bit SEH lowering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241829 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAllow {e,r}bp as the target of {read,write}_register.
Pat Gavlin [Thu, 9 Jul 2015 17:40:29 +0000 (17:40 +0000)]
Allow {e,r}bp as the target of {read,write}_register.

This patch allows the read_register and write_register intrinsics to
read/write the RBP/EBP registers on X86 iff the targeted register is
the frame pointer for the containing function.

Differential Revision: http://reviews.llvm.org/D10977

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241827 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agofix an invisible bug when combining repeated FP divisors
Sanjay Patel [Thu, 9 Jul 2015 17:28:37 +0000 (17:28 +0000)]
fix an invisible bug when combining repeated FP divisors

This patch fixes bugs that were exposed by the addition of fast-math-flags in the DAG:
r237046 ( http://reviews.llvm.org/rL237046 ):

1. When replacing a division node, it's not enough to RAUW.
   We should call CombineTo() to delete dead nodes and combine again.
2. Because we are changing the DAG, we can't return an empty SDValue
   after the transform. As the code comments say:

    Visitation implementation - Implement dag node combining for different node types.
    The semantics are as follows: Return Value:
      SDValue.getNode() == 0 - No change was made
      SDValue.getNode() == N - N was replaced, is dead and has been handled.
      otherwise - N should be replaced by the returned Operand.

The new test case shows no difference with or without this patch, but it will crash if
we re-apply r237046 or enable FMF via the current -enable-fmf-dag cl::opt.

Differential Revision: http://reviews.llvm.org/D9893

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241826 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[StackMap] Use lambdas to specify the sort and erase conditions. NFC.
Juergen Ributzka [Thu, 9 Jul 2015 17:11:15 +0000 (17:11 +0000)]
[StackMap] Use lambdas to specify the sort and erase conditions. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241823 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[StackMap] Rename variables to be more consistent. NFC.
Juergen Ributzka [Thu, 9 Jul 2015 17:11:11 +0000 (17:11 +0000)]
[StackMap] Rename variables to be more consistent. NFC.

Rename a few variables and use auto for long iterator names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241822 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[StackMaps] Use emplace_back when possible. NFC.
Juergen Ributzka [Thu, 9 Jul 2015 17:11:08 +0000 (17:11 +0000)]
[StackMaps] Use emplace_back when possible. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241821 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd a test of a regression discovered during testing of r241673
Silviu Baranga [Thu, 9 Jul 2015 16:40:25 +0000 (16:40 +0000)]
Add a test of a regression discovered during testing of r241673

Summary:
We were missing a corner case where DepCands was not available,
but we were using DepCands to compute the checking pointer
groups.

This adds a test for that regression.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11068

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241818 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one use
Tom Stellard [Thu, 9 Jul 2015 16:30:36 +0000 (16:30 +0000)]
AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one use

This is convered by existing testcases and will be exposed by a future
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241817 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()
Tom Stellard [Thu, 9 Jul 2015 16:30:27 +0000 (16:30 +0000)]
AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()

No test case for this.  I ran into it while working on some improvements
to SIShrinkInstructions.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241816 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd missing file from previous commit.
Rafael Espindola [Thu, 9 Jul 2015 15:58:22 +0000 (15:58 +0000)]
Add missing file from previous commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241815 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoBasic support for BSD symbol tables in archives.
Rafael Espindola [Thu, 9 Jul 2015 15:56:23 +0000 (15:56 +0000)]
Basic support for BSD symbol tables in archives.

This could be optimized and for now we only produce __.SYMDEF
and not "__.SYMDEF SORTED".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241814 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Add missing preamble to a source file
Krzysztof Parzyszek [Thu, 9 Jul 2015 15:40:25 +0000 (15:40 +0000)]
[Hexagon] Add missing preamble to a source file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241813 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove redundant variable. NFC.
Rafael Espindola [Thu, 9 Jul 2015 15:24:39 +0000 (15:24 +0000)]
Remove redundant variable. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241810 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDon't rely on the DepCands iteration order when constructing checking pointer groups
Silviu Baranga [Thu, 9 Jul 2015 15:18:25 +0000 (15:18 +0000)]
Don't rely on the DepCands iteration order when constructing checking pointer groups

Summary:
The checking pointer group construction algorithm relied on the iteration on DepCands.
We would need the same leaders across runs and the same iteration order over the underlying std::set for determinism.

This changes the algorithm to process the pointers in the order in which they were added to the runtime check, which is deterministic.
We need to update the tests, since the order in which pointers appear has changed.

No new tests were added, since it is impossible to test for non-determinism.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11064

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241809 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd a helper to printing BE of LE depending on the format.
Rafael Espindola [Thu, 9 Jul 2015 15:13:41 +0000 (15:13 +0000)]
Add a helper to printing BE of LE depending on the format.

The gnu ar format uses BE numbers. The BSD one uses LE. Add a helper for one or the
other. NFC for now, just removes some noise from the following patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241808 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRe-instate the EVT parameter to getScalarShiftAmountTy() for OOT user
Mehdi Amini [Thu, 9 Jul 2015 15:12:23 +0000 (15:12 +0000)]
Re-instate the EVT parameter to getScalarShiftAmountTy() for OOT user

A documentation for this function would be nice by the way.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241807 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReapply fixed r241790: Fix shift legalization and lowering for big constants.
Pawel Bylica [Thu, 9 Jul 2015 14:58:04 +0000 (14:58 +0000)]
Reapply fixed r241790: Fix shift legalization and lowering for big constants.

Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt.

Reviewers: nadav, majnemer, sanjoy, RKSimon

Subscribers: RKSimon, llvm-commits

Differential Revision: http://reviews.llvm.org/D10767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241806 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoExtract printBSDMemberHeader.
Rafael Espindola [Thu, 9 Jul 2015 14:54:12 +0000 (14:54 +0000)]
Extract printBSDMemberHeader.

It will get another use in the following patch. Also rename the other helper to
printGNUSmallMemberHeader for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241805 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Hexagon] Add support for atomic RMW operations
Krzysztof Parzyszek [Thu, 9 Jul 2015 14:51:21 +0000 (14:51 +0000)]
[Hexagon] Add support for atomic RMW operations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241804 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AArch64] Select SBFIZ or UBFIZ instead of left + right shifts
Arnaud A. de Grandmaison [Thu, 9 Jul 2015 14:33:38 +0000 (14:33 +0000)]
[AArch64] Select SBFIZ or UBFIZ instead of left + right shifts

And rename LSB to Immr / MSB to Imms to match the ARM ARM terminology.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241803 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ARM] Thumb1 3 to 2 operand convertion for commutative operations
Scott Douglass [Thu, 9 Jul 2015 14:13:55 +0000 (14:13 +0000)]
[ARM] Thumb1 3 to 2 operand convertion for commutative operations

Differential Revision: http://reviews.llvm.org/D11057

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241802 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ARM] Don't be overzealous converting Thumb1 3 to 2 operands
Scott Douglass [Thu, 9 Jul 2015 14:13:48 +0000 (14:13 +0000)]
[ARM] Don't be overzealous converting Thumb1 3 to 2 operands

Differential Revision: http://reviews.llvm.org/D11056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241801 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2
Scott Douglass [Thu, 9 Jul 2015 14:13:41 +0000 (14:13 +0000)]
[ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2

Differential Revision: http://reviews.llvm.org/D11055

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241800 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ARM] Refactor converting Thumb1 from 3 to 2 operand (nfc)
Scott Douglass [Thu, 9 Jul 2015 14:13:34 +0000 (14:13 +0000)]
[ARM] Refactor converting Thumb1 from 3 to 2 operand (nfc)

Also adds some test cases.

Differential Revision: http://reviews.llvm.org/D11054

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241799 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ARM] Add ADD tests for Thumb2 narrowing (nfc)
Scott Douglass [Thu, 9 Jul 2015 14:13:22 +0000 (14:13 +0000)]
[ARM] Add ADD tests for Thumb2 narrowing (nfc)

Differential Revision: http://reviews.llvm.org/D11053

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241798 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTest for 241794 (nest attribute in AArch64)
Renato Golin [Thu, 9 Jul 2015 13:29:35 +0000 (13:29 +0000)]
Test for 241794 (nest attribute in AArch64)

Forgot to git add the test.

Patch by Stephen Cross.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241797 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd support for nest attribute to AArch64 backend
Renato Golin [Thu, 9 Jul 2015 10:18:02 +0000 (10:18 +0000)]
Add support for nest attribute to AArch64 backend

The nest attribute is currently supported on the x86 (32-bit) and x86-64
backends, but not on ARM (32-bit) or AArch64. This patch adds support for
nest to the AArch64 backend.

Register x18 is used by GCC for this purpose and hence is used here.
As discussed on the GCC mailing list the register choice is an ABI issue
and so choosing the same register as GCC means __builtin_call_with_static_chain
is compatible.

Patch by Stephen Cross.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241794 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd getSizeInBits function to the APFloat class
Tamas Berghammer [Thu, 9 Jul 2015 10:13:39 +0000 (10:13 +0000)]
Add getSizeInBits function to the APFloat class

The newly added function returns the size of the specified floating
point semantics in bits.

Differential revision: http://reviews.llvm.org/D8413

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241793 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert r241790: Fix shift legalization and lowering for big constants.
Pawel Bylica [Thu, 9 Jul 2015 09:50:54 +0000 (09:50 +0000)]
Revert r241790: Fix shift legalization and lowering for big constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241792 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix shift legalization and lowering for big constants.
Pawel Bylica [Thu, 9 Jul 2015 08:01:36 +0000 (08:01 +0000)]
Fix shift legalization and lowering for big constants.

Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt.

Reviewers: nadav, majnemer, sanjoy, RKSimon

Subscribers: RKSimon, llvm-commits

Differential Revision: http://reviews.llvm.org/D10767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241790 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoExtended syntax of vector version of getelementptr instruction.
Elena Demikhovsky [Thu, 9 Jul 2015 07:42:48 +0000 (07:42 +0000)]
Extended syntax of vector version of getelementptr instruction.

The justification of this change is here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-March/082989.html

According to the current GEP syntax, vector GEP requires that each index must be a vector with the same number of elements.

%A = getelementptr i8, <4 x i8*> %ptrs, <4 x i64> %offsets

In this implementation I let each index be or vector or scalar. All vector indices must have the same number of elements. The scalar value will mean the splat vector value.

(1) %A = getelementptr i8, i8* %ptr, <4 x i64> %offsets
or
(2) %A = getelementptr i8, <4 x i8*> %ptrs, i64 %offset

In all cases the %A type is <4 x i8*>

In the case (2) we add the same offset to all pointers.

The case (1) covers C[B[i]] case, when we have the same base C and different offsets B[i].

The documentation is updated.

http://reviews.llvm.org/D10496

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241788 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LAA] Fix line break in comment
Adam Nemet [Thu, 9 Jul 2015 06:47:21 +0000 (06:47 +0000)]
[LAA] Fix line break in comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241785 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LAA] Rename IsRTNeeded to IsRTCheckAnalysisNeeded
Adam Nemet [Thu, 9 Jul 2015 06:47:18 +0000 (06:47 +0000)]
[LAA] Rename IsRTNeeded to IsRTCheckAnalysisNeeded

The original name was too close to NeedRTCheck which is what the actual
memcheck analysis returns.  This flag, as the new name suggests, is only
used to whether to initiate that analysis.

Also a comment is added to answer one question I had about this code for
a long time.  Namely, how does this flag differ from
isDependencyCheckNeeded since they are seemingly set at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241784 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agollvm-readobj: Fix an unused variable after r241764
Justin Bogner [Thu, 9 Jul 2015 04:27:36 +0000 (04:27 +0000)]
llvm-readobj: Fix an unused variable after r241764

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241783 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTemporarily reverting 241765, 241768, and 241772 to unbreak the build bots.
Adrian Prantl [Thu, 9 Jul 2015 02:14:49 +0000 (02:14 +0000)]
Temporarily reverting 241765, 241768, and 241772 to unbreak the build bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241781 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove getDataLayout() from TargetSelectionDAGInfo (had no users)
Mehdi Amini [Thu, 9 Jul 2015 02:10:08 +0000 (02:10 +0000)]
Remove getDataLayout() from TargetSelectionDAGInfo (had no users)

Summary:
Remove empty subclass in the process.

This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren, ted

Differential Revision: http://reviews.llvm.org/D11045

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241780 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove getDataLayout() from TargetLowering
Mehdi Amini [Thu, 9 Jul 2015 02:09:52 +0000 (02:09 +0000)]
Remove getDataLayout() from TargetLowering

Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11042

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241779 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMake isLegalAddressingMode() taking DataLayout as an argument
Mehdi Amini [Thu, 9 Jul 2015 02:09:40 +0000 (02:09 +0000)]
Make isLegalAddressingMode() taking DataLayout as an argument

Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11040

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241778 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMake getByValTypeAlignment() taking DataLayout as an argument
Mehdi Amini [Thu, 9 Jul 2015 02:09:28 +0000 (02:09 +0000)]
Make getByValTypeAlignment() taking DataLayout as an argument

Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11038

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241777 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMake TargetLowering::getShiftAmountTy() taking DataLayout as an argument
Mehdi Amini [Thu, 9 Jul 2015 02:09:20 +0000 (02:09 +0000)]
Make TargetLowering::getShiftAmountTy() taking DataLayout as an argument

Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11037

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241776 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMake TargetLowering::getPointerTy() taking DataLayout as an argument
Mehdi Amini [Thu, 9 Jul 2015 02:09:04 +0000 (02:09 +0000)]
Make TargetLowering::getPointerTy() taking DataLayout as an argument

Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, ted, yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11028

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241775 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMake TargetTransformInfo keeping a reference to the Module DataLayout
Mehdi Amini [Thu, 9 Jul 2015 02:08:42 +0000 (02:08 +0000)]
Make TargetTransformInfo keeping a reference to the Module DataLayout

DataLayout is no longer optional. It was initialized with or without
a DataLayout, and the DataLayout when supplied could have been the
one from the TargetMachine.

Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11021

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241774 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRedirect DataLayout from TargetMachine to Module in ComputeValueVTs()
Mehdi Amini [Thu, 9 Jul 2015 01:57:34 +0000 (01:57 +0000)]
Redirect DataLayout from TargetMachine to Module in ComputeValueVTs()

Summary:
Avoid using the TargetMachine owned DataLayout and use the Module owned
one instead. This requires passing the DataLayout up the stack to
ComputeValueVTs().

This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11019

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241773 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSilence a warning, trying to unbreak the build after r241765.
Davide Italiano [Thu, 9 Jul 2015 01:45:02 +0000 (01:45 +0000)]
Silence a warning, trying to unbreak the build after r241765.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241772 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix typename issues.
Michael J. Spencer [Thu, 9 Jul 2015 00:46:24 +0000 (00:46 +0000)]
Fix typename issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241768 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Object][ELF] Support dumping hash-tables from files with no section table.
Michael J. Spencer [Thu, 9 Jul 2015 00:21:06 +0000 (00:21 +0000)]
[Object][ELF] Support dumping hash-tables from files with no section table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241765 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[CodeView] Add support for emitting column information
David Majnemer [Thu, 9 Jul 2015 00:19:51 +0000 (00:19 +0000)]
[CodeView] Add support for emitting column information

Column information is present in CodeView when the line table subsection
has bit 0 set to 1 in it's flags field.  The column information is
represented as a pair of 16-bit quantities: a starting and ending
column.  This information is present at the end of the chunk, after all
the line-PC pairs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241764 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LAA] Fix misleading use of word 'consecutive'
Adam Nemet [Thu, 9 Jul 2015 00:03:22 +0000 (00:03 +0000)]
[LAA] Fix misleading use of word 'consecutive'

Fix some places where the word consecutive is used but the code really
means constant-stride (i.e. not just unit stride).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241763 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMIR Serialization: Serialize the 'undef' register machine operand flag.
Alex Lorenz [Wed, 8 Jul 2015 23:58:31 +0000 (23:58 +0000)]
MIR Serialization: Serialize the 'undef' register machine operand flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241762 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SLPVectorizer] Try different vectorization factors for store chains
Sanjay Patel [Wed, 8 Jul 2015 23:40:55 +0000 (23:40 +0000)]
[SLPVectorizer] Try different vectorization factors for store chains
...and set max vector register size based on target

This patch is based on discussion on the llvmdev mailing list:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-July/087405.html

and also solves:
https://llvm.org/bugs/show_bug.cgi?id=17170

Several FIXME/TODO items are noted in comments as potential improvements.

Differential Revision: http://reviews.llvm.org/D10950

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241760 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRegisterPressure: Add PressureDiff::dump()
Matthias Braun [Wed, 8 Jul 2015 23:40:27 +0000 (23:40 +0000)]
RegisterPressure: Add PressureDiff::dump()

Also display the pressure diff in the case of a
getMaxUpwardPressureDelta() verify failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241759 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LAA] Revert a small part of r239295
Adam Nemet [Wed, 8 Jul 2015 22:58:48 +0000 (22:58 +0000)]
[LAA] Revert a small part of r239295

This commit ([LAA] Fix estimation of number of memchecks) regressed the
logic a bit.  We shouldn't quit the analysis if we encounter a pointer
without known bounds *unless* we actually need to emit a memcheck for
it.

The original code was using NumComparisons which is now computed
differently.  Instead I compute NeedRTCheck from NumReadPtrChecks and
NumWritePtrChecks.

As side note, I find the separation of NeedRTCheck and CanDoRT
confusing, so I will try to merge them in a follow-up patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241756 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRun clang-format before making changes to StackMaps. NFC.
Juergen Ributzka [Wed, 8 Jul 2015 22:42:09 +0000 (22:42 +0000)]
Run clang-format before making changes to StackMaps. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241754 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert part of "Disallow Archive::child_iterator that don't point to an archive."
Rafael Espindola [Wed, 8 Jul 2015 22:41:41 +0000 (22:41 +0000)]
Revert part of "Disallow Archive::child_iterator that don't point to an archive."

This reverts parts of commit r241747. MSVC doesn't like it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241753 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[x86] enable machine combiner reassociations for scalar single-precision multiplies
Sanjay Patel [Wed, 8 Jul 2015 22:35:20 +0000 (22:35 +0000)]
[x86] enable machine combiner reassociations for scalar single-precision multiplies

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241752 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDon't reject an archive with just a symbol table.
Rafael Espindola [Wed, 8 Jul 2015 22:27:54 +0000 (22:27 +0000)]
Don't reject an archive with just a symbol table.

It is pretty unambiguous how to interpret it and gnu ar accepts it too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241750 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDisallow Archive::child_iterator that don't point to an archive.
Rafael Espindola [Wed, 8 Jul 2015 22:15:07 +0000 (22:15 +0000)]
Disallow Archive::child_iterator that don't point to an archive.

NFC, just less error prone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241747 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LoopVectorizer] Rename BypassBlock to VectorPH, and CheckBlock to NewVectorPH. NFCI.
Michael Zolotukhin [Wed, 8 Jul 2015 21:48:03 +0000 (21:48 +0000)]
[LoopVectorizer] Rename BypassBlock to VectorPH, and CheckBlock to NewVectorPH. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241742 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LoopVectorizer] Restructurize code for emitting RT checks. NFCI.
Michael Zolotukhin [Wed, 8 Jul 2015 21:47:59 +0000 (21:47 +0000)]
[LoopVectorizer] Restructurize code for emitting RT checks. NFCI.

Place all code corresponding to a run-time check in one place.
Previously we generated some code, then proceeded to a next check, then
finished the code for the first check (like splitting blocks and
generating branches). Now the code for generating a check is
self-contained.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241741 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LoopVectorizer] Remove redundant variables PastOverflowCheck and OverflowCheckAnchor...
Michael Zolotukhin [Wed, 8 Jul 2015 21:47:56 +0000 (21:47 +0000)]
[LoopVectorizer] Remove redundant variables PastOverflowCheck and OverflowCheckAnchor. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241740 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LoopVectorizer] Move some code around to ease further refactoring. NFCI.
Michael Zolotukhin [Wed, 8 Jul 2015 21:47:53 +0000 (21:47 +0000)]
[LoopVectorizer] Move some code around to ease further refactoring. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241739 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LoopVectorizer] Remove redundant variable LastBypassBlock. NFC.
Michael Zolotukhin [Wed, 8 Jul 2015 21:47:47 +0000 (21:47 +0000)]
[LoopVectorizer] Remove redundant variable LastBypassBlock. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241738 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMIR Parser: Remove redundant TODO comment. NFC.
Alex Lorenz [Wed, 8 Jul 2015 21:30:21 +0000 (21:30 +0000)]
MIR Parser: Remove redundant TODO comment. NFC.

This TODO comment has been redundant since r240474.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241737 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd tests for the NVPTXLowerAggrCopies pass.
Eli Bendersky [Wed, 8 Jul 2015 21:29:28 +0000 (21:29 +0000)]
Add tests for the NVPTXLowerAggrCopies pass.

Note: not testing memmove lowering for now, as it's broken
[see https://llvm.org/bugs/show_bug.cgi?id=24056]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241736 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMIR Serialization: Serialize the 'killed' register machine operand flag.
Alex Lorenz [Wed, 8 Jul 2015 21:23:34 +0000 (21:23 +0000)]
MIR Serialization: Serialize the 'killed' register machine operand flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241734 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd missing dependency to Hexagon target.
Diego Novillo [Wed, 8 Jul 2015 21:13:37 +0000 (21:13 +0000)]
Add missing dependency to Hexagon target.

A recent patch added calls to isInstructionTriviallyDead without the
corresponding dependency on TransformUtils.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241731 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][SSE] Vector shift test cleanup. NFC.
Simon Pilgrim [Wed, 8 Jul 2015 21:11:17 +0000 (21:11 +0000)]
[X86][SSE] Vector shift test cleanup. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241730 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse a raw_svector_ostream and simplify a loop. NFC.
Rafael Espindola [Wed, 8 Jul 2015 21:07:18 +0000 (21:07 +0000)]
Use a raw_svector_ostream and simplify a loop. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241727 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Win64] Only treat some functions as having the Win64 convention
Reid Kleckner [Wed, 8 Jul 2015 21:03:47 +0000 (21:03 +0000)]
[Win64] Only treat some functions as having the Win64 convention

All the usual X86 target-specific conventions are collapsed to the
normal Win64 convention, but the custom conventions like GHC and webkit
should not be.

Previously we would assume that the caller allocated 32 bytes of shadow
space for us, which is not how webkit_jscc or other custom conventions
are supposed to work.

Based on a patch by peavo@outlook.com.

Fixes PR24051.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241725 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoStart adding support for writing archives in BSD format.
Rafael Espindola [Wed, 8 Jul 2015 20:47:32 +0000 (20:47 +0000)]
Start adding support for writing archives in BSD format.

No support for the symbol table yet (but will hopefully add it today).
We always use the long filename format so that we can align the member,
which is an advantage of the BSD format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241721 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMIR Parser: Use source locations for MBB naming errors.
Alex Lorenz [Wed, 8 Jul 2015 20:22:20 +0000 (20:22 +0000)]
MIR Parser: Use source locations for MBB naming errors.

This commit changes the type of the field 'Name' in the struct
'yaml::MachineBasicBlock' from 'std::string' to 'yaml::StringValue'. This change
allows the MIR parser to report errors related to the MBB name with the proper
source locations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241718 91177308-0d34-0410-b5e6-96231b3b80d8