Hooray, everyone now uses the same printBasicBlockLabel implementation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28056 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28055 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a now-dead method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28054 91177308-0d34-0410-b5e6-96231b3b80d8

There is no reason to use a virtual method to store this word.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28053 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the debug machine code emitter.  The "FilePrinterEmitter" is moreuseful for debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28052 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the debug machine code emitter.  The "FilePrinterEmitter" is more
useful for debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28051 91177308-0d34-0410-b5e6-96231b3b80d8

Extend printBasicBlockLabel a bit so that it can be used to print all
basic block labels, consolidating the code to do so in one place for each
target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28050 91177308-0d34-0410-b5e6-96231b3b80d8

Update the PPC compilation callback code to not need weird abi-violating
prologs and epilogs, keep all the asm in one place, and remove use of
compiler builtin functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28049 91177308-0d34-0410-b5e6-96231b3b80d8

Add pass ID's for various passes, so they can be AddRequiredID.  Patch by
Domagoj Babic!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28048 91177308-0d34-0410-b5e6-96231b3b80d8

De-virtualize SwitchSection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28047 91177308-0d34-0410-b5e6-96231b3b80d8

De-virtualize EmitZeroes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28046 91177308-0d34-0410-b5e6-96231b3b80d8

Finish support for Microsoft ML/MASM.  May still be a few rough edges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28045 91177308-0d34-0410-b5e6-96231b3b80d8

Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28044 91177308-0d34-0410-b5e6-96231b3b80d8

Put instruction names into the first non TargetInstrInfo namespace found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28043 91177308-0d34-0410-b5e6-96231b3b80d8

New testcase that crashes the new CFE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28042 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a latent bug that my spiller patch last week exposed: we were leaving
instructions in the virtregfolded map that were deleted.  Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map.  The solution is to remove entries
from the map when we delete the instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28041 91177308-0d34-0410-b5e6-96231b3b80d8

When promoting a load to a reg-reg copy, where the load was a previous
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28040 91177308-0d34-0410-b5e6-96231b3b80d8

Remove previous patch, which wasn't quite right.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28039 91177308-0d34-0410-b5e6-96231b3b80d8

instructions can be in different namespaces.  Make sure to use the right
one for each instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28038 91177308-0d34-0410-b5e6-96231b3b80d8

Put PHI/INLINEASM into the correct namespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28037 91177308-0d34-0410-b5e6-96231b3b80d8

Formating

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28036 91177308-0d34-0410-b5e6-96231b3b80d8

Dis-favor stores more

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28035 91177308-0d34-0410-b5e6-96231b3b80d8

Bottom up register-pressure reduction scheduler now pushes store operations
up the schedule. This helps code that looks like this:

loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...

Without this change, the stores and computations are more likely to
interleave:

loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...

This can increase the number of spills if we are unlucky.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28033 91177308-0d34-0410-b5e6-96231b3b80d8

Mark instructions whose pattern is (store ...) isStore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28032 91177308-0d34-0410-b5e6-96231b3b80d8

Didn't mean ScheduleDAGList.cpp to make the last checkin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28030 91177308-0d34-0410-b5e6-96231b3b80d8

Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28029 91177308-0d34-0410-b5e6-96231b3b80d8

Intel mode no longer uses %'s on registers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28028 91177308-0d34-0410-b5e6-96231b3b80d8

Remove %'s from register names when in intel mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28027 91177308-0d34-0410-b5e6-96231b3b80d8

Format #APP lines a bit nicer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28026 91177308-0d34-0410-b5e6-96231b3b80d8

Local spiller kills a store if the folded restore is turned into a copy.
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28024 91177308-0d34-0410-b5e6-96231b3b80d8

Mingw32 patches supplied by Anton Korobeynikov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28023 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a bogus transformation.  This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
with some changes I have to the new CFE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28022 91177308-0d34-0410-b5e6-96231b3b80d8

I can't spell: Register, not Regsiter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28021 91177308-0d34-0410-b5e6-96231b3b80d8

Implemented x86 inline asm b, h, w, k modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28020 91177308-0d34-0410-b5e6-96231b3b80d8

Fix InstCombine/2006-04-28-ShiftShiftLongLong.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28019 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase miscompiled by instcombine

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28018 91177308-0d34-0410-b5e6-96231b3b80d8

Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28017 91177308-0d34-0410-b5e6-96231b3b80d8

testcase that crashes the ppc backend, which can't sextinreg(i1)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28016 91177308-0d34-0410-b5e6-96231b3b80d8

Initial caller side support (for CCC only, not FastCC) of 128-bit vector
passing by value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28015 91177308-0d34-0410-b5e6-96231b3b80d8

Bare-bone X86 inline asm printer support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28014 91177308-0d34-0410-b5e6-96231b3b80d8

Update. It should use two shufps, not three!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28013 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the temporary option: -no-isel-fold-inflight

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28012 91177308-0d34-0410-b5e6-96231b3b80d8

Implement four-wide shuffle with 2 shufps if no more than two elements come
from each vector. e.g.
        shuffle(G1, G2, 7, 1, 5, 2)
==>
        movaps _G2, %xmm0
        shufps $151, _G1, %xmm0
        shufps $216, %xmm0, %xmm0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28011 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR743: emit -help output of a tool to cout, not cerr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28010 91177308-0d34-0410-b5e6-96231b3b80d8

TargetLowering::LowerArguments should return a VBIT_CONVERT of
FORMAL_ARGUMENTS SDOperand in the return result vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28009 91177308-0d34-0410-b5e6-96231b3b80d8

Mapping of physregs can make it so that the designated and input physregs are
the same.  In this case, don't emit a noop copy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28008 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Transforms/Reassociate/2006-04-27-ReassociateVector.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28007 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28006 91177308-0d34-0410-b5e6-96231b3b80d8

Use movaps instead of movapd for spill / restore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28005 91177308-0d34-0410-b5e6-96231b3b80d8

Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
node can be folded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28003 91177308-0d34-0410-b5e6-96231b3b80d8

When isel'ing a node, mark its operands "InFlight" before selecting them. These
nodes should not be folded into other nodes.
This fixes the miscompilation of PR 749.
Temporarily under flag control.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28002 91177308-0d34-0410-b5e6-96231b3b80d8

When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy.  This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write.  As one example, this change does:

        pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
        xorps %XMM2, %XMM5
        cmpltps %XMM1, %XMM0
-       movaps XMMWORD PTR [%ESP + 52], %XMM0
-       movapd %XMM6, XMMWORD PTR [%ESP + 52]
+       movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
        movapd XMMWORD PTR [%ESP + 52], %XMM6
        movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
        cmpltps %XMM3, %XMM0
-       movaps XMMWORD PTR [%ESP + 20], %XMM0
-       movapd %XMM7, XMMWORD PTR [%ESP + 20]
+       movaps %XMM7, %XMM0
        cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
        movapd XMMWORD PTR [%ESP + 20], %XMM7
        cmpltps %XMM4, %XMM0

... which is far better than a store followed by a load!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28001 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for PR748

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28000 91177308-0d34-0410-b5e6-96231b3b80d8

Add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27999 91177308-0d34-0410-b5e6-96231b3b80d8

Add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27998 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for inserting undef into a vector.  This implements
Transforms/InstCombine/vec_insert_to_shuffle.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27997 91177308-0d34-0410-b5e6-96231b3b80d8

This should turn into one vector shuffle instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27996 91177308-0d34-0410-b5e6-96231b3b80d8

Make x86 isel lowering produce tailcall nodes. They are match to normal calls
for now.

Patch contributed by Alexander Friedman.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27994 91177308-0d34-0410-b5e6-96231b3b80d8

A couple of new entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27993 91177308-0d34-0410-b5e6-96231b3b80d8

Support for passing 128-bit vector arguments via XMM registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27992 91177308-0d34-0410-b5e6-96231b3b80d8

Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
(VAND, VADD, etc.). Legalizer will assert otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27991 91177308-0d34-0410-b5e6-96231b3b80d8

For PR747:
If we fail to find a required program, simply set that program to echo
out something that tells the user the situation. That is, instead of just
"true runtest" we now get "echo 'Skipped: runtest not found'".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27990 91177308-0d34-0410-b5e6-96231b3b80d8

Oops

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27989 91177308-0d34-0410-b5e6-96231b3b80d8

Bug fix: not updating NumIntRegs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27988 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and
PR748.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27987 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27986 91177308-0d34-0410-b5e6-96231b3b80d8

- Clean up formal argument lowering code. Prepare for vector pass by value work.
- Fixed vararg support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27985 91177308-0d34-0410-b5e6-96231b3b80d8

Fix some nondeterminstic behavior in the mem2reg pass that (in addition to
nondeterminism being bad) could cause some trivial missed optimizations (dead
phi nodes being left around for later passes to clean up).

With this, llvm-gcc4 now bootstraps and correctly compares.  I don't know
why I never tried to do it before... :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27984 91177308-0d34-0410-b5e6-96231b3b80d8

Actually, semantical doesn't appear to be a word.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27983 91177308-0d34-0410-b5e6-96231b3b80d8

Implement Transforms/IndVarsSimplify/complex-scev.ll, a case where we didn't
recognize some simple affine IV's.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27982 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27981 91177308-0d34-0410-b5e6-96231b3b80d8

Fix fastcc failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27980 91177308-0d34-0410-b5e6-96231b3b80d8

Unfortunately this really isn't the place for advertisement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27979 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27978 91177308-0d34-0410-b5e6-96231b3b80d8

Fix some anchors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27977 91177308-0d34-0410-b5e6-96231b3b80d8

Add some notes about the current state of source (front end) languages
so we can point to them on llvm-dev.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27976 91177308-0d34-0410-b5e6-96231b3b80d8

Switching over FORMAL_ARGUMENTS mechanism to lower call arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27975 91177308-0d34-0410-b5e6-96231b3b80d8

Don't forget return void.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27974 91177308-0d34-0410-b5e6-96231b3b80d8

Keep the stack from on darwin 16-byte aligned.  This fixes many JIT
failres.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27973 91177308-0d34-0410-b5e6-96231b3b80d8

Separate LowerOperation() into multiple functions, one per opcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27972 91177308-0d34-0410-b5e6-96231b3b80d8

slightly more useful error message

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27971 91177308-0d34-0410-b5e6-96231b3b80d8

better c99 struct handling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27970 91177308-0d34-0410-b5e6-96231b3b80d8

another c99 style problem

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27969 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27968 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27967 91177308-0d34-0410-b5e6-96231b3b80d8

No functionality changes, but cleaner code with correct comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27966 91177308-0d34-0410-b5e6-96231b3b80d8

Explicitly specify result type for def : Pat<> patterns (if it produces a vector
result). Otherwise tblgen will pick the default (v16i8 for 128-bit vector).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27965 91177308-0d34-0410-b5e6-96231b3b80d8

Added X86 SSE2 intrinsics which can be represented as vector_shuffles. This is
a temporary workaround for the 2-wide vector_shuffle problem (i.e. its mask
would have type v2i32 which is not legal).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27964 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27963 91177308-0d34-0410-b5e6-96231b3b80d8

Added a movq test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27962 91177308-0d34-0410-b5e6-96231b3b80d8

Special case handling two wide build_vector(0, x).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27961 91177308-0d34-0410-b5e6-96231b3b80d8

Some missing movlps, movhps, movlpd, and movhpd patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27960 91177308-0d34-0410-b5e6-96231b3b80d8

A little bit more build_vector enhancement for v8i16 cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27959 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a completed entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27958 91177308-0d34-0410-b5e6-96231b3b80d8

Suggest looking at the SPARC backend.  How weird is that?? :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27957 91177308-0d34-0410-b5e6-96231b3b80d8

Added addJumpTableIndex

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27956 91177308-0d34-0410-b5e6-96231b3b80d8

MakeMIInst() should handle jump table index operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27955 91177308-0d34-0410-b5e6-96231b3b80d8

Add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27954 91177308-0d34-0410-b5e6-96231b3b80d8

MOVL shuffle (i.e. movd or movss / movsd from memory) of undef, V2 == V2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27953 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the updating of the machine CFG when a PHI node was in a successor of
the jump table's range check block.  This re-enables 100% dense jump tables
by default on PPC & x86

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27952 91177308-0d34-0410-b5e6-96231b3b80d8