Simplify some code now that the RHS of a rem can't be 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26413 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26412 91177308-0d34-0410-b5e6-96231b3b80d8

Rearrange some code, fold "rem X, 0", implementing rem.ll:test6

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26411 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for output memory constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26410 91177308-0d34-0410-b5e6-96231b3b80d8

Qualify dwarf namespace inside llvm namespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26409 91177308-0d34-0410-b5e6-96231b3b80d8

readme updates

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26405 91177308-0d34-0410-b5e6-96231b3b80d8

Partial enabling of functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26404 91177308-0d34-0410-b5e6-96231b3b80d8

Don't print constant initializers, they may span lines now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26403 91177308-0d34-0410-b5e6-96231b3b80d8

Supporting multiple compile units.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26402 91177308-0d34-0410-b5e6-96231b3b80d8

Re-orging file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26401 91177308-0d34-0410-b5e6-96231b3b80d8

Pretty print large struct constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26400 91177308-0d34-0410-b5e6-96231b3b80d8

Removed dependency on how operands are printed (want multi-line.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26399 91177308-0d34-0410-b5e6-96231b3b80d8

Use -emit-llvm -S to get .ll file output from llvm-gcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26397 91177308-0d34-0410-b5e6-96231b3b80d8

Merge two almost-identical pieces of code.

Make this code more powerful by using ComputeMaskedBits instead of looking
for an AND operand.  This lets us fold this:

int %test23(int %a) {
        %tmp.1 = and int %a, 1
        %tmp.2 = seteq int %tmp.1, 0
        %tmp.3 = cast bool %tmp.2 to int  ;; xor tmp1, 1
        ret int %tmp.3
}

into: xor (and a, 1), 1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26396 91177308-0d34-0410-b5e6-96231b3b80d8

new testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26395 91177308-0d34-0410-b5e6-96231b3b80d8

Fold (A^B) == A  ->  B == 0
and  (A-B) == A  ->  B == 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26394 91177308-0d34-0410-b5e6-96231b3b80d8

New testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26393 91177308-0d34-0410-b5e6-96231b3b80d8

Implement bit propagation through sub nodes, this (re)implements
PowerPC/div-2.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26392 91177308-0d34-0410-b5e6-96231b3b80d8

Reenable this

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26391 91177308-0d34-0410-b5e6-96231b3b80d8

remove some completed notes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26390 91177308-0d34-0410-b5e6-96231b3b80d8

Check RHS simplification before LHS simplification to avoid infinitely looping
on PowerPC/small-arguments.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26389 91177308-0d34-0410-b5e6-96231b3b80d8

Just like we use the RHS of an AND to simplify the LHS, use the LHS to
simplify the RHS.  This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:

_test2:
        srwi r2, r3, 1
        xori r3, r2, 40961
        blr

instead of this:

_test2:
        rlwinm r2, r3, 31, 17, 31
        xori r2, r2, 40961
        rlwinm r3, r2, 0, 16, 31
        blr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26388 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26387 91177308-0d34-0410-b5e6-96231b3b80d8

Add a bunch of missed cases.  Perhaps the most significant of which is that
assertzext produces zero bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26386 91177308-0d34-0410-b5e6-96231b3b80d8

Fold (X|C1)^C2 -> X^(C1|C2) when possible.  This implements
InstCombine/or.ll:test23.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26385 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26384 91177308-0d34-0410-b5e6-96231b3b80d8

Reverting. Didn't realize some developers were embedding constants in their
target assembler code gen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26383 91177308-0d34-0410-b5e6-96231b3b80d8

ConstantPoolIndex is now the displacement portion of the address (rather
than base).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26382 91177308-0d34-0410-b5e6-96231b3b80d8

Print ConstantPoolSDNode offset field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26381 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
and 2005-05-12-Int64ToFP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26380 91177308-0d34-0410-b5e6-96231b3b80d8

Format large struct constants for readability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26379 91177308-0d34-0410-b5e6-96231b3b80d8

New test case: use lea for imul by some constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26378 91177308-0d34-0410-b5e6-96231b3b80d8

lea.ll is XFAIL until we implement convertToThreeAddress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26377 91177308-0d34-0410-b5e6-96231b3b80d8

* Cleaned up addressing mode matching code.
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
  they need to be matched before LEA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26376 91177308-0d34-0410-b5e6-96231b3b80d8

Updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26375 91177308-0d34-0410-b5e6-96231b3b80d8

* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
* Add patterns to handle GlobalAddress, ConstantPool, etc.
  MOV32ri to materialize these nodes in registers.
  ADD32ri to handle %reg + GA, etc.
  MOV32mi to handle store GA, etc. to memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26374 91177308-0d34-0410-b5e6-96231b3b80d8

ConstantPoolIndex is now the displacement field of addressing mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26373 91177308-0d34-0410-b5e6-96231b3b80d8

Added a common about the need for X86ISD::Wrapper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26372 91177308-0d34-0410-b5e6-96231b3b80d8

Added an offset field to ConstantPoolSDNode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26371 91177308-0d34-0410-b5e6-96231b3b80d8

this fails, mark it as such

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26370 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug that Evan exposed with some changes he's making, and that was
exposed with a fastcc problem (breaking pcompress2 on x86 with -enable-x86-fastcc).

When reloading a reused reg, make sure to invalidate the reloaded reg, and
check to see if there are any other pending uses of the same register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26369 91177308-0d34-0410-b5e6-96231b3b80d8

Remove debugging printout :)

Add a minor compile time win, no codegen change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26368 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor some code from being inline to being out in a new class with methods.
This gets rid of two gotos, which is always nice, and also adds some comments.

No functionality change, this is just a refactor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26367 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an obvious bug exposed when we are doing
ADD X, 4
==>
MOV32ri $X+4, ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26366 91177308-0d34-0410-b5e6-96231b3b80d8

Add memory printing support for PPC.  Input memory operands now work with
inline asms! :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26365 91177308-0d34-0410-b5e6-96231b3b80d8

Use the PrintAsmMemoryOperand to print addressing modes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26364 91177308-0d34-0410-b5e6-96231b3b80d8

Add a PrintAsmMemoryOperand method for printing addresses

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26363 91177308-0d34-0410-b5e6-96231b3b80d8

Pass all the flags to the asm printer, not just the # operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26362 91177308-0d34-0410-b5e6-96231b3b80d8

rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.

Add support for addressing modes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26361 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor operand adding out to a new AddOperand method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26358 91177308-0d34-0410-b5e6-96231b3b80d8

add a method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26357 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a problem that Nate noticed that boils down to an over conservative check
in the code that does "select C, (X+Y), (X-Y) --> (X+(select C, Y, (-Y)))".
We now compile this loop:

LBB1_1: ; no_exit
        add r6, r2, r3
        subf r3, r2, r3
        cmpwi cr0, r2, 0
        addi r7, r5, 4
        lwz r2, 0(r5)
        addi r4, r4, 1
        blt cr0, LBB1_4 ; no_exit
LBB1_3: ; no_exit
        mr r3, r6
LBB1_4: ; no_exit
        cmpwi cr0, r4, 16
        mr r5, r7
        bne cr0, LBB1_1 ; no_exit

into this instead:

LBB1_1: ; no_exit
        srawi r6, r2, 31
        add r2, r2, r6
        xor r6, r2, r6
        addi r7, r5, 4
        lwz r2, 0(r5)
        addi r4, r4, 1
        add r3, r3, r6
        cmpwi cr0, r4, 16
        mr r5, r7
        bne cr0, LBB1_1 ; no_exit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26356 91177308-0d34-0410-b5e6-96231b3b80d8

Add pointer and reference types.  Added short-term code to ignore NULL types
(to allow llvm-gcc4 to build.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26355 91177308-0d34-0410-b5e6-96231b3b80d8

Get VC++ building again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26351 91177308-0d34-0410-b5e6-96231b3b80d8

Implement (most of) selection of inline asm memory operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26350 91177308-0d34-0410-b5e6-96231b3b80d8

Select inline asm memory operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26349 91177308-0d34-0410-b5e6-96231b3b80d8

Implement selection of inline asm memory operands

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26348 91177308-0d34-0410-b5e6-96231b3b80d8

Add some hooks for selecting memory addresses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26347 91177308-0d34-0410-b5e6-96231b3b80d8

Lower C_Memory operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26346 91177308-0d34-0410-b5e6-96231b3b80d8

Recognize memory operand codes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26345 91177308-0d34-0410-b5e6-96231b3b80d8

Add C_Memory operand type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26344 91177308-0d34-0410-b5e6-96231b3b80d8

Parse the %*# constraint modifiers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26341 91177308-0d34-0410-b5e6-96231b3b80d8

add a new flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26340 91177308-0d34-0410-b5e6-96231b3b80d8

Added basic support for typedefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26339 91177308-0d34-0410-b5e6-96231b3b80d8

PPC JIT relocation model should be DynamicNoPIC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26338 91177308-0d34-0410-b5e6-96231b3b80d8

- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
  and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
  mentioned leaf nodes. Do not mutate and nodes and do not record the
  selection in CodeGenMap. These nodes should be safe to duplicate. This is
  a performance win.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26335 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an endianness problem on big-endian targets with expanded operands
to inline asms.  Mark some methods const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26334 91177308-0d34-0410-b5e6-96231b3b80d8

Implement the PPC inline asm "L" modifier.  This allows us to compile:

long long test(long long X) {
  __asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
  return X;
}

to:
        foo r2 r3 r2 r3

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26333 91177308-0d34-0410-b5e6-96231b3b80d8

Record all of the expanded registers in the DAG and machine instr, fixing
several bugs in inline asm expanded operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26332 91177308-0d34-0410-b5e6-96231b3b80d8

DwarfWriter reading basic type information from llvm-gcc4 code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26331 91177308-0d34-0410-b5e6-96231b3b80d8

Match the case of other mailing lists in the list

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26330 91177308-0d34-0410-b5e6-96231b3b80d8

document the llvm-testresults list

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26329 91177308-0d34-0410-b5e6-96231b3b80d8

Code cleanups, no functionality change

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26328 91177308-0d34-0410-b5e6-96231b3b80d8

"." isn't enough to get a private label on linux, use ".L".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26327 91177308-0d34-0410-b5e6-96231b3b80d8

add a small and simple case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26326 91177308-0d34-0410-b5e6-96231b3b80d8

A couple of new entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26325 91177308-0d34-0410-b5e6-96231b3b80d8

PIC related bug fixes.
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26324 91177308-0d34-0410-b5e6-96231b3b80d8

X86 codegen tweak to use lea in another case:

Suppose base == %eax and it has multiple uses, then instead of
  movl %eax, %ecx
  addl $8, %ecx
use
  leal 8(%eax), %ecx.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26323 91177308-0d34-0410-b5e6-96231b3b80d8

Add a test case for 'lea'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26322 91177308-0d34-0410-b5e6-96231b3b80d8

Missing .globl for weak / link-once .text symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26321 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Regression/Transforms/LoopUnswitch/2006-02-22-UnswitchCrash.ll, which
caused SPASS to fail building last night.

We can't trivially unswitch a loop if the exit block has phi nodes in it,
because we don't know which predecessor to use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26320 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase distilled from SPASS

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26319 91177308-0d34-0410-b5e6-96231b3b80d8

This fixes a couple of problems with expansion

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26318 91177308-0d34-0410-b5e6-96231b3b80d8

Don't return registers from register classes that aren't legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26317 91177308-0d34-0410-b5e6-96231b3b80d8

Change a whole bunch of code to be built around RegsForValue instead of
a single register number.  This fully implements promotion for inline asms,
expand is close but not quite right yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26316 91177308-0d34-0410-b5e6-96231b3b80d8

- Added option -relocation-model to set relocation model. Valid values include static, pic,
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8

Coordinate activities with llvm-gcc4 and dwarf.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26314 91177308-0d34-0410-b5e6-96231b3b80d8

Make the LLVM headers "-ansi -pedantic -Wno-long-long" clean.

Patch by Martin Partel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26313 91177308-0d34-0410-b5e6-96231b3b80d8

Turn on loop unswitching tonight

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26312 91177308-0d34-0410-b5e6-96231b3b80d8

Add some comments, simplify some code, and fix a bug that caused rewriting
to rewrite with the wrong value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26311 91177308-0d34-0410-b5e6-96231b3b80d8

Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
Fixed some existing bugs (wrong predicates, prefixes) at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26310 91177308-0d34-0410-b5e6-96231b3b80d8

reorder some libraries

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26309 91177308-0d34-0410-b5e6-96231b3b80d8

split register class handling from explicit physreg handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8

expose the set of values types holdable in a regclass to clients

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26307 91177308-0d34-0410-b5e6-96231b3b80d8

Adjust to changes in getRegForInlineAsmConstraint prototype

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26306 91177308-0d34-0410-b5e6-96231b3b80d8

Updates to match change of getRegForInlineAsmConstraint prototype

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8

Pass in a value type to getRegForInlineAsmConstraint, allowing targets to
select different sets of registers depending on the type requested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26304 91177308-0d34-0410-b5e6-96231b3b80d8

One more round of reorg so sabre doesn't freak out. :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26303 91177308-0d34-0410-b5e6-96231b3b80d8

A big more cleaning up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26302 91177308-0d34-0410-b5e6-96231b3b80d8

Moving things to their proper places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26301 91177308-0d34-0410-b5e6-96231b3b80d8